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Dive into the research topics where Tarik Graba is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Jitter Compensation Mechanism for Dynamic Deterministic Networks
Soudais, G., Graba, T., Mathieu, Y. & Bigo, S., 1 Jan 2023, 2023 Optical Fiber Communications Conference and Exhibition, OFC 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Th3D.2. (2023 Optical Fiber Communications Conference and Exhibition, OFC 2023 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Diffusional Side-Channel Leakage from Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE
Yli-Mayry, V., Ueno, R., Miura, N., Nagata, M., Bhasin, S., Mathieu, Y., Graba, T., Danger, J. L. & Homma, N., 1 Jan 2021, In: IEEE Transactions on Information Forensics and Security. 16, p. 1351-1364 14 p., 9238027.Research output: Contribution to journal › Article › peer-review
Open Access -
RSM protection of the present lightweight cipher as a RISC-V extension
Tehrani, E., Graba, T., Merabet, A. S. & Danger, J. L., 1 Jan 2021, Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021. Leporati, F., Vitabile, S. & Skavhaug, A. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 325-332 8 p. (Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
Ueno, R., Homma, N., Morioka, S., Miura, N., Matsuda, K., Nagata, M., Bhasin, S., Mathieu, Y., Graba, T. & Danger, J. L., 1 Apr 2020, In: IEEE Transactions on Computers. 69, 4, p. 534-548 15 p., 8922779.Research output: Contribution to journal › Article › peer-review
Open Access -
RISC-V Extension for Lightweight Cryptography
Tehrani, E., Graba, T., Merabet, A. S. & Danger, J. L., 1 Aug 2020, Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Trost, A., Zemva, A. & Skavhaug, A. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 222-228 7 p. 9217866. (Proceedings - Euromicro Conference on Digital System Design, DSD 2020).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Classification of lightweight block ciphers for specific processor accelerated implementations
Tehrani, E., Graba, T., Merabet, A. S., Guilley, S. & Danger, J. L., 1 Nov 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. Institute of Electrical and Electronics Engineers Inc., p. 747-750 4 p. 8965156. (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Generic architecture for lightweight block ciphers: A first step towards agile implementation of multiple ciphers
Tehrani, E., Danger, J. L. & Graba, T., 1 Jan 2019, Information Security Theory and Practice - 12th IFIP WG 11.2 International Conference, WISTP 2018, Revised Selected Papers. Yeun, C. Y. & Blazy, O. (eds.). Springer Verlag, p. 28-43 16 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 11469 LNCS).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Open Access -
Analysis of mixed PUF-TRNG circuit based on SR-Latches in FD-SOI technology
Danger, J. L., Yashiro, R., Graba, T., Mathieu, Y., Si-Merabet, A., Sakiyama, K., Miura, N., Nagata, M. & Guilley, S., 12 Oct 2018, Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. Konofaos, N., Novotny, M. & Skavhaug, A. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 508-515 8 p. 8491861. (Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor
Miura, N., Matsuda, K., Nagata, M., Bhasin, S., Yli-Mayry, V., Homma, N., Mathieu, Y., Graba, T. & Danger, J. L., 10 Aug 2017, 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., p. C266-C267 8008502. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
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Cryptographically Secure Shield for Security IPs Protection
Ngo, X. T., Danger, J. L., Guilley, S., Graba, T., Mathieu, Y., Najm, Z. & Bhasin, S., 1 Feb 2017, In: IEEE Transactions on Computers. 66, 2, p. 354-360 7 p., 7498620.Research output: Contribution to journal › Article › peer-review