3D multiprocessor with 3D NoC architecture based on Tezzaron technology

M. H. Jabbar; D. Houzet; O. Hammami

doi:10.1109/3DIC.2012.6263027

3D multiprocessor with 3D NoC architecture based on Tezzaron technology

M. H. Jabbar, D. Houzet, O. Hammami

Institut National Polytechnique de Grenoble (INPG)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we describe the architecture and implementation of 3D multiprocessor with 3D NoC. The 2 tiers design is based on 16 processors communicating using a 4x2 mesh NoC and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. Due to the limitation when investigating NoC performance using simulation, the purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D.

Original language	English
Title of host publication	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOIs	https://doi.org/10.1109/3DIC.2012.6263027
Publication status	Published - 1 Dec 2011
Event	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan Duration: 31 Jan 2012 → 2 Feb 2012

Publication series

Name	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Conference

Conference	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
Country/Territory	Japan
City	Osaka
Period	31/01/12 → 2/02/12

Keywords

3D IC
3D NoC
MPSoC
Tezzaron

Access to Document

10.1109/3DIC.2012.6263027

Cite this

@inproceedings{10a86fee6c214f83ad373bed8a097408,

title = "3D multiprocessor with 3D NoC architecture based on Tezzaron technology",

abstract = "In this paper, we describe the architecture and implementation of 3D multiprocessor with 3D NoC. The 2 tiers design is based on 16 processors communicating using a 4x2 mesh NoC and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. Due to the limitation when investigating NoC performance using simulation, the purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D.",

keywords = "3D IC, 3D NoC, MPSoC, Tezzaron",

author = "Jabbar, \{M. H.\} and D. Houzet and O. Hammami",

year = "2011",

month = dec,

day = "1",

doi = "10.1109/3DIC.2012.6263027",

language = "English",

isbn = "9781467321891",

series = "2011 IEEE International 3D Systems Integration Conference, 3DIC 2011",

booktitle = "2011 IEEE International 3D Systems Integration Conference, 3DIC 2011",

note = "2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 ; Conference date: 31-01-2012 Through 02-02-2012",

}

Jabbar, MH, Houzet, D & Hammami, O 2011, 3D multiprocessor with 3D NoC architecture based on Tezzaron technology. in 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011., 6263027, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, Osaka, Japan, 31/01/12. https://doi.org/10.1109/3DIC.2012.6263027

3D multiprocessor with 3D NoC architecture based on Tezzaron technology. / Jabbar, M. H.; Houzet, D.; Hammami, O.
2011 IEEE International 3D Systems Integration Conference, 3DIC 2011. 2011. 6263027 (2011 IEEE International 3D Systems Integration Conference, 3DIC 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - 3D multiprocessor with 3D NoC architecture based on Tezzaron technology

AU - Jabbar, M. H.

AU - Houzet, D.

AU - Hammami, O.

PY - 2011/12/1

Y1 - 2011/12/1

N2 - In this paper, we describe the architecture and implementation of 3D multiprocessor with 3D NoC. The 2 tiers design is based on 16 processors communicating using a 4x2 mesh NoC and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. Due to the limitation when investigating NoC performance using simulation, the purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D.

AB - In this paper, we describe the architecture and implementation of 3D multiprocessor with 3D NoC. The 2 tiers design is based on 16 processors communicating using a 4x2 mesh NoC and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. Due to the limitation when investigating NoC performance using simulation, the purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D.

KW - 3D IC

KW - 3D NoC

KW - MPSoC

KW - Tezzaron

U2 - 10.1109/3DIC.2012.6263027

DO - 10.1109/3DIC.2012.6263027

M3 - Conference contribution

AN - SCOPUS:84866842080

SN - 9781467321891

T3 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

BT - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

T2 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Y2 - 31 January 2012 through 2 February 2012

ER -

3D multiprocessor with 3D NoC architecture based on Tezzaron technology

Abstract

Publication series

Conference

Keywords

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