A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΔΣ ADC

Chadi Jabbour; David Camarero; Tam Nguyen Van; Patrick Loumeau

doi:10.1109/ISCAS.2009.5118066

A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΔΣ ADC

Chadi Jabbour
, David Camarero
, Tam Nguyen Van
, Patrick Loumeau

CNRS LTCI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Citations (Scopus)

Abstract

This paper presents a reconfigurable High-Pass (HP) Time-Interleaved (TI) Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) from theoretical and practical points of view. This ADC is designed to fulfill the requirements of GSM, UMTS, WiFi and WiMAX standards. The reconfiguration is performed by adjusting the interpolation factor, the ΔΣ modulator order and the number of active channels thereby allowing bandwidth-resolution trade-off as well as bandwith-power consumption trade-off. The circuit has been fabricated in a 1 V 65 nm CMOS process. Clocked at 50 MHz, the prototype chip consumes 6 mW per channel and the core die area is 2.52 mm².

Original language	English
Title of host publication	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1557-1560
Number of pages	4
ISBN (Print)	9781424438280
DOIs	https://doi.org/10.1109/ISCAS.2009.5118066
Publication status	Published - 1 Jan 2009
Externally published	Yes
Event	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan, Province of China Duration: 24 May 2009 → 27 May 2009

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Country/Territory	Taiwan, Province of China
City	Taipei
Period	24/05/09 → 27/05/09

Access to Document

10.1109/ISCAS.2009.5118066

Cite this

Jabbour, C., Camarero, D., Van, T. N., & Loumeau, P. (2009). A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΔΣ ADC. In 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 (pp. 1557-1560). Article 5118066 (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2009.5118066

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title = "A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΔΣ ADC",

abstract = "This paper presents a reconfigurable High-Pass (HP) Time-Interleaved (TI) Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) from theoretical and practical points of view. This ADC is designed to fulfill the requirements of GSM, UMTS, WiFi and WiMAX standards. The reconfiguration is performed by adjusting the interpolation factor, the ΔΣ modulator order and the number of active channels thereby allowing bandwidth-resolution trade-off as well as bandwith-power consumption trade-off. The circuit has been fabricated in a 1 V 65 nm CMOS process. Clocked at 50 MHz, the prototype chip consumes 6 mW per channel and the core die area is 2.52 mm2.",

author = "Chadi Jabbour and David Camarero and Van, \{Tam Nguyen\} and Patrick Loumeau",

year = "2009",

month = jan,

day = "1",

doi = "10.1109/ISCAS.2009.5118066",

language = "English",

isbn = "9781424438280",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1557--1560",

booktitle = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009",

note = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 ; Conference date: 24-05-2009 Through 27-05-2009",

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Jabbour, C, Camarero, D, Van, TN & Loumeau, P 2009, A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΔΣ ADC. in 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009., 5118066, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 1557-1560, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, Province of China, 24/05/09. https://doi.org/10.1109/ISCAS.2009.5118066

A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΔΣ ADC. / Jabbour, Chadi; Camarero, David; Van, Tam Nguyen et al.
2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. Institute of Electrical and Electronics Engineers Inc., 2009. p. 1557-1560 5118066 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Y1 - 2009/1/1

N2 - This paper presents a reconfigurable High-Pass (HP) Time-Interleaved (TI) Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) from theoretical and practical points of view. This ADC is designed to fulfill the requirements of GSM, UMTS, WiFi and WiMAX standards. The reconfiguration is performed by adjusting the interpolation factor, the ΔΣ modulator order and the number of active channels thereby allowing bandwidth-resolution trade-off as well as bandwith-power consumption trade-off. The circuit has been fabricated in a 1 V 65 nm CMOS process. Clocked at 50 MHz, the prototype chip consumes 6 mW per channel and the core die area is 2.52 mm2.

AB - This paper presents a reconfigurable High-Pass (HP) Time-Interleaved (TI) Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) from theoretical and practical points of view. This ADC is designed to fulfill the requirements of GSM, UMTS, WiFi and WiMAX standards. The reconfiguration is performed by adjusting the interpolation factor, the ΔΣ modulator order and the number of active channels thereby allowing bandwidth-resolution trade-off as well as bandwith-power consumption trade-off. The circuit has been fabricated in a 1 V 65 nm CMOS process. Clocked at 50 MHz, the prototype chip consumes 6 mW per channel and the core die area is 2.52 mm2.

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DO - 10.1109/ISCAS.2009.5118066

M3 - Conference contribution

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SN - 9781424438280

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Jabbour C, Camarero D, Van TN, Loumeau P. A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΔΣ ADC. In 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. Institute of Electrical and Electronics Engineers Inc. 2009. p. 1557-1560. 5118066. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2009.5118066

A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΔΣ ADC

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