A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor

Noriyuki Miura; Kohei Matsuda; Makoto Nagata; Shivam Bhasin; Ville Yli-Mayry; Naofumi Homma; Yves Mathieu; Tarik Graba; Jean Luc Danger

doi:10.23919/VLSIC.2017.8008502

A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor

Noriyuki Miura
, Kohei Matsuda
, Makoto Nagata
, Shivam Bhasin
, Ville Yli-Mayry
, Naofumi Homma
, Yves Mathieu
, Tarik Graba
, Jean Luc Danger

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.

Original language	English
Title of host publication	2017 Symposium on VLSI Circuits, VLSI Circuits 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C266-C267
ISBN (Electronic)	9784863486065
DOIs	https://doi.org/10.23919/VLSIC.2017.8008502
Publication status	Published - 10 Aug 2017
Event	31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan Duration: 5 Jun 2017 → 8 Jun 2017

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	31st Symposium on VLSI Circuits, VLSI Circuits 2017
Country/Territory	Japan
City	Kyoto
Period	5/06/17 → 8/06/17

Access to Document

10.23919/VLSIC.2017.8008502

Cite this

Miura, N., Matsuda, K., Nagata, M., Bhasin, S., Yli-Mayry, V., Homma, N., Mathieu, Y., Graba, T., & Danger, J. L. (2017). A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 (pp. C266-C267). Article 8008502 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2017.8008502

@inproceedings{f74410e86bab4573af77853fbe7da215,

title = "A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor",

abstract = "An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.",

author = "Noriyuki Miura and Kohei Matsuda and Makoto Nagata and Shivam Bhasin and Ville Yli-Mayry and Naofumi Homma and Yves Mathieu and Tarik Graba and Danger, \{Jean Luc\}",

note = "Publisher Copyright: {\textcopyright} 2017 JSAP.; 31st Symposium on VLSI Circuits, VLSI Circuits 2017 ; Conference date: 05-06-2017 Through 08-06-2017",

year = "2017",

month = aug,

day = "10",

doi = "10.23919/VLSIC.2017.8008502",

language = "English",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "C266--C267",

booktitle = "2017 Symposium on VLSI Circuits, VLSI Circuits 2017",

}

Miura, N, Matsuda, K, Nagata, M, Bhasin, S, Yli-Mayry, V, Homma, N, Mathieu, Y, Graba, T & Danger, JL 2017, A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor. in 2017 Symposium on VLSI Circuits, VLSI Circuits 2017., 8008502, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. C266-C267, 31st Symposium on VLSI Circuits, VLSI Circuits 2017, Kyoto, Japan, 5/06/17. https://doi.org/10.23919/VLSIC.2017.8008502

A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor. / Miura, Noriyuki; Matsuda, Kohei; Nagata, Makoto et al.
2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. C266-C267 8008502 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor

AU - Miura, Noriyuki

AU - Matsuda, Kohei

AU - Nagata, Makoto

AU - Bhasin, Shivam

AU - Yli-Mayry, Ville

AU - Homma, Naofumi

AU - Mathieu, Yves

AU - Graba, Tarik

AU - Danger, Jean Luc

PY - 2017/8/10

Y1 - 2017/8/10

N2 - An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.

AB - An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.

U2 - 10.23919/VLSIC.2017.8008502

DO - 10.23919/VLSIC.2017.8008502

M3 - Conference contribution

AN - SCOPUS:85034015368

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - C266-C267

BT - 2017 Symposium on VLSI Circuits, VLSI Circuits 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 31st Symposium on VLSI Circuits, VLSI Circuits 2017

Y2 - 5 June 2017 through 8 June 2017

ER -

Miura N, Matsuda K, Nagata M, Bhasin S, Yli-Mayry V, Homma N et al. A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. C266-C267. 8008502. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSIC.2017.8008502