A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture

Benoit Larras; Paul Chollet; Cyril Lahuec; Fabrice Seguin; Matthieu Arzel

doi:10.1109/ISCAS.2017.8050658

A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture

Benoit Larras
, Paul Chollet
, Cyril Lahuec
, Fabrice Seguin
, Matthieu Arzel

Université de Lille
LAB-STICC

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

To operate under severe energy constraints, clique-based neural networks are good candidates. They benefit from a reduced exchange of information between low-complexity processing units with no performance degradation. This paper proposes a modular, flexible and scalable architecture validated by an ST 65-nm CMOS ASIC implementation for a 30-neuron clique-based neural network circuit. With 0.8V power supply, 150nA unitary current and a low performance degradation, the neuron energy consumption is reduced to only 7fJ per synaptic event. The network occupies a 41,820μm2 silicon area.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems
Subtitle of host publication	From Dreams to Innovation, ISCAS 2017 - Conference Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467368520
DOIs	https://doi.org/10.1109/ISCAS.2017.8050658
Publication status	Published - 25 Sept 2017
Event	2017 IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States Duration: 28 May 2017 → 31 May 2017

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	0
ISSN (Print)	0271-4310

Conference

Conference	2017 IEEE International Symposium on Circuits and Systems, ISCAS 2017
Country/Territory	United States
City	Baltimore
Period	28/05/17 → 31/05/17

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/ISCAS.2017.8050658

Cite this

Larras, B., Chollet, P., Lahuec, C., Seguin, F., & Arzel, M. (2017). A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings Article 8050658 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 0). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2017.8050658

Larras, Benoit ; Chollet, Paul ; Lahuec, Cyril et al. / A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture. IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{0f9330ae2c054c1ba149c143ead90186,

title = "A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture",

abstract = "To operate under severe energy constraints, clique-based neural networks are good candidates. They benefit from a reduced exchange of information between low-complexity processing units with no performance degradation. This paper proposes a modular, flexible and scalable architecture validated by an ST 65-nm CMOS ASIC implementation for a 30-neuron clique-based neural network circuit. With 0.8V power supply, 150nA unitary current and a low performance degradation, the neuron energy consumption is reduced to only 7fJ per synaptic event. The network occupies a 41,820μm2 silicon area.",

author = "Benoit Larras and Paul Chollet and Cyril Lahuec and Fabrice Seguin and Matthieu Arzel",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE International Symposium on Circuits and Systems, ISCAS 2017 ; Conference date: 28-05-2017 Through 31-05-2017",

year = "2017",

month = sep,

day = "25",

doi = "10.1109/ISCAS.2017.8050658",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "IEEE International Symposium on Circuits and Systems",

}

Larras, B, Chollet, P, Lahuec, C, Seguin, F & Arzel, M 2017, A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture. in IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings., 8050658, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 0, Institute of Electrical and Electronics Engineers Inc., 2017 IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 28/05/17. https://doi.org/10.1109/ISCAS.2017.8050658

A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture. / Larras, Benoit; Chollet, Paul; Lahuec, Cyril et al.
IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. 8050658 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 0).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture

AU - Larras, Benoit

AU - Chollet, Paul

AU - Lahuec, Cyril

AU - Seguin, Fabrice

AU - Arzel, Matthieu

PY - 2017/9/25

Y1 - 2017/9/25

N2 - To operate under severe energy constraints, clique-based neural networks are good candidates. They benefit from a reduced exchange of information between low-complexity processing units with no performance degradation. This paper proposes a modular, flexible and scalable architecture validated by an ST 65-nm CMOS ASIC implementation for a 30-neuron clique-based neural network circuit. With 0.8V power supply, 150nA unitary current and a low performance degradation, the neuron energy consumption is reduced to only 7fJ per synaptic event. The network occupies a 41,820μm2 silicon area.

AB - To operate under severe energy constraints, clique-based neural networks are good candidates. They benefit from a reduced exchange of information between low-complexity processing units with no performance degradation. This paper proposes a modular, flexible and scalable architecture validated by an ST 65-nm CMOS ASIC implementation for a 30-neuron clique-based neural network circuit. With 0.8V power supply, 150nA unitary current and a low performance degradation, the neuron energy consumption is reduced to only 7fJ per synaptic event. The network occupies a 41,820μm2 silicon area.

U2 - 10.1109/ISCAS.2017.8050658

DO - 10.1109/ISCAS.2017.8050658

M3 - Conference contribution

AN - SCOPUS:85032662349

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 IEEE International Symposium on Circuits and Systems, ISCAS 2017

Y2 - 28 May 2017 through 31 May 2017

ER -

Larras B, Chollet P, Lahuec C, Seguin F, Arzel M. A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. 8050658. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2017.8050658

A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture

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