A defect-tolerant multiplexer using differential logic for FPGAs

As the dimensions of CMOS devices scale down to the nanometers, manufacturing defects are becoming a challenging concern in current and future technologies. This work aims at improving defect tolerance in FPGAs which are certainly affected by technology downsizing. Since the cornerstone of the FPGA logic and interconnect resources is the multiplexer, we propose a defect-tolerant multiplexer architecture based on differential logic. This architecture proved to be more resilient to single defects (opens and bridges) than its single-ended standard counterpart and more compact than existing hardened architectures. The architectures were studied under single defect injection by a tool that models several possible defects for a given design according to its extracted netlist. Eventually, the robustness gain using differential logic was assessed for different sizes of FPGA look-up tables.