TY - GEN
T1 - A Front-End Test Stand for the Analog ASICs of the ATLAS LAr Calorimeter HL-LHC Upgrade
AU - Liu, H.
AU - Chen, H.
AU - Chen, K.
AU - De Geronimo, G.
AU - De La Taille, C.
AU - Lanni, F.
AU - Ma, H.
AU - Morange, N.
AU - Seguin-Moreau, N.
AU - Serin, L.
AU - Simion, S.
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2018/11/12
Y1 - 2018/11/12
N2 - This paper describes the development of a common front-end test stand for the analog ASICs, which are part of the effort to develop the front-end electronics for the ATLAS LAr calorimeter HL-LHC (High Luminosity LHC) upgrade. The common test stand consists of the front-end test board, toy calorimeters, ASIC mezzanine boards and the DAQ system. The front-end test board is the bridge between the DAQ system and the ASIC mezzanine, it integrates two 16-channel ADCs for digitizing the outputs of the analog ASIC and a calibration pulse generator for detector signal injection. The analog ASICs under test are mounted on the ASIC mezzanine boards, their outputs are connected to the front-end test board through an FMC connector. A Xilinx ZC706 evaluation board is utilized as the DAQ board for this test stand, a Gigabit Ethernet link is implemented on the DAQ board for slow control, configuration and ADC data transmission. The tests of two front-end analog ASICs with this test stand are ongoing. The preliminary test results demonstrated that this test stand is suitable for the testing of the multi-channel analog ASICs developed for the LAr Calorimeter HL-LHC upgrade.
AB - This paper describes the development of a common front-end test stand for the analog ASICs, which are part of the effort to develop the front-end electronics for the ATLAS LAr calorimeter HL-LHC (High Luminosity LHC) upgrade. The common test stand consists of the front-end test board, toy calorimeters, ASIC mezzanine boards and the DAQ system. The front-end test board is the bridge between the DAQ system and the ASIC mezzanine, it integrates two 16-channel ADCs for digitizing the outputs of the analog ASIC and a calibration pulse generator for detector signal injection. The analog ASICs under test are mounted on the ASIC mezzanine boards, their outputs are connected to the front-end test board through an FMC connector. A Xilinx ZC706 evaluation board is utilized as the DAQ board for this test stand, a Gigabit Ethernet link is implemented on the DAQ board for slow control, configuration and ADC data transmission. The tests of two front-end analog ASICs with this test stand are ongoing. The preliminary test results demonstrated that this test stand is suitable for the testing of the multi-channel analog ASICs developed for the LAr Calorimeter HL-LHC upgrade.
UR - https://www.scopus.com/pages/publications/85058456735
U2 - 10.1109/NSSMIC.2017.8532654
DO - 10.1109/NSSMIC.2017.8532654
M3 - Conference contribution
AN - SCOPUS:85058456735
T3 - 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2017 - Conference Proceedings
BT - 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2017 - Conference Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2017
Y2 - 21 October 2017 through 28 October 2017
ER -