A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology

Noise-immunity of a logic gate or a circuit is now an important design criterion with dimension scaling to nanometers. Two noise-immune design structures based on Markov random field (MRF) have been proposed in [1], [2] and [3]. These design structures can achieve an excellent noise-immunity but with a large number of redundant transistors. In this paper, a general noise-immune design structure easy to implement has been proposed. It can achieve nearly the same noise-immunity as Master-and-Slave MRF (MAS MRF) [3] but with a significantly less area penalty. Basic logic gates are simulated and comparison of different circuits based on different design structures is presented. These simulations are based on the Berkeley Predictive Technology Model (BPTM) 65nm CMOS Technology [4] and ST 65nm CMOS models.