TY - GEN
T1 - A loosely synchronizing asynchronous router for TDM-scheduled NOCs
AU - Kotleas, I.
AU - Humphreys, D.
AU - Sørensen, R. B.
AU - Kasapaki, E.
AU - Brandner, F.
AU - Sparsø, J.
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2015/1/13
Y1 - 2015/1/13
N2 - This paper presents an asynchronous router design for use in time-division-multiplexed (TDM) networks-on-chip. Unlike existing synchronous, mesochronous and asynchronous router designs with similar functionality, the router is able to silently skip over cycles/TDM-slots where no traffic is scheduled and hence avoid all switching activity in the idle links and router ports. In this way switching activity is reduced to the minimum possible amount. The fact that this relaxed synchronization is sufficient to implement TDM scheduling represents a contribution at the conceptual level. The idea can only be implemented using asynchronous circuit techniques. To this end, the paper explores the use of "click-element" templates. Click-element templates use only flip-flops and conventional gates, and this greatly simplifies the design process when using conventional EDA tools and standard cell libraries. Few papers, if any, have explored this.
AB - This paper presents an asynchronous router design for use in time-division-multiplexed (TDM) networks-on-chip. Unlike existing synchronous, mesochronous and asynchronous router designs with similar functionality, the router is able to silently skip over cycles/TDM-slots where no traffic is scheduled and hence avoid all switching activity in the idle links and router ports. In this way switching activity is reduced to the minimum possible amount. The fact that this relaxed synchronization is sufficient to implement TDM scheduling represents a contribution at the conceptual level. The idea can only be implemented using asynchronous circuit techniques. To this end, the paper explores the use of "click-element" templates. Click-element templates use only flip-flops and conventional gates, and this greatly simplifies the design process when using conventional EDA tools and standard cell libraries. Few papers, if any, have explored this.
U2 - 10.1109/NOCS.2014.7008774
DO - 10.1109/NOCS.2014.7008774
M3 - Conference contribution
AN - SCOPUS:84922566556
T3 - Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014
SP - 151
EP - 158
BT - Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014
A2 - Bertozzi, Davide
A2 - Benini, Luca
A2 - Yalamanchili, Sudhakar
A2 - Henkel, Joerg
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014
Y2 - 17 September 2014 through 19 September 2014
ER -