A LP/HP UMTS/GSM σ δ ADC suited for a Zero-IF/Low-IF receiver

Chadi Jabbour; Hasham Khushk; Hussein Fakhoury; Van Tam Nguyen; Patrick Loumeau

doi:10.1109/ISCAS.2011.5937768

A LP/HP UMTS/GSM σ δ ADC suited for a Zero-IF/Low-IF receiver

Chadi Jabbour
, Hasham Khushk
, Hussein Fakhoury
, Van Tam Nguyen
, Patrick Loumeau

CNRS LTCI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents the design of a reconfigurable Delta Sigma Analog to Digital Converter (ADC). Its main degree of liberty is the choice of the noise shaping among low pass and high pass. This reconfiguration parameter allows it to be adapted for both the Low-IF and the Zero-If receiver architectures. The ADC is GSM/UMTS compliant. It was designed in a 1.2 V 65 nm CMOS process. Electrical simulation results showed a SNDR of 84 dB for the GSM mode with a Low-IF frequency of 19.2 MHz and a SNDR of 77.4 dB for the UMTS at DC.

Original language	English
Title of host publication	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Pages	1125-1128
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2011.5937768
Publication status	Published - 2 Aug 2011
Externally published	Yes
Event	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil Duration: 15 May 2011 → 18 May 2011

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Country/Territory	Brazil
City	Rio de Janeiro
Period	15/05/11 → 18/05/11

Keywords

Analog to Digital Converter
Delta Sigma
Low-IF/Zero-IF receiver
Reconfiguration

Access to Document

10.1109/ISCAS.2011.5937768

Cite this

@inproceedings{25e22f9b682c459c9b197e24befeebe2,

title = "A LP/HP UMTS/GSM σ δ ADC suited for a Zero-IF/Low-IF receiver",

abstract = "This paper presents the design of a reconfigurable Delta Sigma Analog to Digital Converter (ADC). Its main degree of liberty is the choice of the noise shaping among low pass and high pass. This reconfiguration parameter allows it to be adapted for both the Low-IF and the Zero-If receiver architectures. The ADC is GSM/UMTS compliant. It was designed in a 1.2 V 65 nm CMOS process. Electrical simulation results showed a SNDR of 84 dB for the GSM mode with a Low-IF frequency of 19.2 MHz and a SNDR of 77.4 dB for the UMTS at DC.",

keywords = "Analog to Digital Converter, Delta Sigma, Low-IF/Zero-IF receiver, Reconfiguration",

author = "Chadi Jabbour and Hasham Khushk and Hussein Fakhoury and Nguyen, \{Van Tam\} and Patrick Loumeau",

year = "2011",

month = aug,

day = "2",

doi = "10.1109/ISCAS.2011.5937768",

language = "English",

isbn = "9781424494736",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "1125--1128",

booktitle = "2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011",

note = "2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 ; Conference date: 15-05-2011 Through 18-05-2011",

}

Jabbour, C, Khushk, H, Fakhoury, H, Nguyen, VT & Loumeau, P 2011, A LP/HP UMTS/GSM σ δ ADC suited for a Zero-IF/Low-IF receiver. in 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011., 5937768, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1125-1128, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, Rio de Janeiro, Brazil, 15/05/11. https://doi.org/10.1109/ISCAS.2011.5937768

A LP/HP UMTS/GSM σ δ ADC suited for a Zero-IF/Low-IF receiver. / Jabbour, Chadi; Khushk, Hasham; Fakhoury, Hussein et al.
2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011. 2011. p. 1125-1128 5937768 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Nguyen, Van Tam

AU - Loumeau, Patrick

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N2 - This paper presents the design of a reconfigurable Delta Sigma Analog to Digital Converter (ADC). Its main degree of liberty is the choice of the noise shaping among low pass and high pass. This reconfiguration parameter allows it to be adapted for both the Low-IF and the Zero-If receiver architectures. The ADC is GSM/UMTS compliant. It was designed in a 1.2 V 65 nm CMOS process. Electrical simulation results showed a SNDR of 84 dB for the GSM mode with a Low-IF frequency of 19.2 MHz and a SNDR of 77.4 dB for the UMTS at DC.

AB - This paper presents the design of a reconfigurable Delta Sigma Analog to Digital Converter (ADC). Its main degree of liberty is the choice of the noise shaping among low pass and high pass. This reconfiguration parameter allows it to be adapted for both the Low-IF and the Zero-If receiver architectures. The ADC is GSM/UMTS compliant. It was designed in a 1.2 V 65 nm CMOS process. Electrical simulation results showed a SNDR of 84 dB for the GSM mode with a Low-IF frequency of 19.2 MHz and a SNDR of 77.4 dB for the UMTS at DC.

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KW - Reconfiguration

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BT - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011

T2 - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011

Y2 - 15 May 2011 through 18 May 2011

ER -

A LP/HP UMTS/GSM σ δ ADC suited for a Zero-IF/Low-IF receiver

Abstract

Publication series

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Keywords

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Cite this