A new fault generator suitable for reliability analysis of digital circuits

Elaine C. Marques, Nilson M. Paiva, Lirida A.B. Naviner, Jean François Naviner

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper deals with fault injection issues for reliability analysis. We propose a fault generator IP suitable for hardware emulation of single and multiple simultaneous faults occurence. The proposed IP is based on a very useful approach that allows the designer to control complexity and completeness of the fault injection process. We provide models for cost and performance estimation of the IP. Also, synthesis results of its implementation on FPGA are given.

Original languageEnglish
Title of host publicationProceedings of the Argentine-Uruguay School of Micro-Nanoelectronics, Technology and Applications 2010, EAMTA 2010
Pages41-45
Number of pages5
Publication statusPublished - 20 Dec 2010
Externally publishedYes
Event4th Argentine School of Micro-Nanoelectronics, Technology and Applications and 1st Uruguay School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2010 - Montevideo, Uruguay
Duration: 1 Oct 20109 Oct 2010

Publication series

NameProceedings of the Argentine-Uruguay School of Micro-Nanoelectronics, Technology and Applications 2010, EAMTA 2010

Conference

Conference4th Argentine School of Micro-Nanoelectronics, Technology and Applications and 1st Uruguay School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2010
Country/TerritoryUruguay
CityMontevideo
Period1/10/109/10/10

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