A new fault-tolerant architecture for CLBs in SRAM-based FPGAs

Arwa Ben Dhia, Lirida Naviner, Philippe Matherat

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This work deals with fault tolerance in digital reconfigurable circuits. We present a novel CLB structure well suited for SRAM-based FPGAs. The proposed solution has a 'Butterfly' shape which embeds intrinsic redundance and is highly regular. The behavior of the proposed Butterfly architecture and that of the conventional one toward bit-inversion errors are compared with a couple of approaches: using Matlab simulations and a fault emulation platform. The Butterfly structure has proved to be more reliable and more tolerant than the conventional counterpart, regardless of the number of simultaneous faults.

Original languageEnglish
Title of host publication2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
Pages761-764
Number of pages4
DOIs
Publication statusPublished - 1 Dec 2012
Externally publishedYes
Event2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 - Seville, Seville, Spain
Duration: 9 Dec 201212 Dec 2012

Publication series

Name2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

Conference

Conference2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
Country/TerritorySpain
CitySeville, Seville
Period9/12/1212/12/12

Keywords

  • Logical masking
  • SRAM-based FPGA
  • fault tolerance
  • reliability analysis

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