A real-time multi-kernel picture convolver

C. Goudet; Y. Mathieu; G. Concordel; N. Demassieux

A real-time multi-kernel picture convolver

C. Goudet
, Y. Mathieu
, G. Concordel
, N. Demassieux

Telecom Paris

Research output: Contribution to journal › Conference article › peer-review

Abstract

The model used for architectural optimization is discussed. It is then shown that the optimal architecture for 2-D convolution uses a 1-D convolution combinatorial operator to reduce the 2-D problem to a classical 1-D systolic array. Furthermore, for a given technology and chip area, if one tries to apply the proposed cost function to this architecture, it is possible to predict a practical bound for the kernel size of convolutions that can be implemented on one chip. Details are given of a 5 × 10 real-time convolver chip that exhibits several new features, including a multikernel mode.

Original language	English
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 1 Dec 1990
Event	Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 - Boston, MA, USA Duration: 13 May 1990 → 16 May 1990

Cite this

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title = "A real-time multi-kernel picture convolver",

abstract = "The model used for architectural optimization is discussed. It is then shown that the optimal architecture for 2-D convolution uses a 1-D convolution combinatorial operator to reduce the 2-D problem to a classical 1-D systolic array. Furthermore, for a given technology and chip area, if one tries to apply the proposed cost function to this architecture, it is possible to predict a practical bound for the kernel size of convolutions that can be implemented on one chip. Details are given of a 5 × 10 real-time convolver chip that exhibits several new features, including a multikernel mode.",

author = "C. Goudet and Y. Mathieu and G. Concordel and N. Demassieux",

year = "1990",

month = dec,

day = "1",

language = "English",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

note = "Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 ; Conference date: 13-05-1990 Through 16-05-1990",

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TY - JOUR

T1 - A real-time multi-kernel picture convolver

AU - Goudet, C.

AU - Mathieu, Y.

AU - Concordel, G.

AU - Demassieux, N.

PY - 1990/12/1

Y1 - 1990/12/1

N2 - The model used for architectural optimization is discussed. It is then shown that the optimal architecture for 2-D convolution uses a 1-D convolution combinatorial operator to reduce the 2-D problem to a classical 1-D systolic array. Furthermore, for a given technology and chip area, if one tries to apply the proposed cost function to this architecture, it is possible to predict a practical bound for the kernel size of convolutions that can be implemented on one chip. Details are given of a 5 × 10 real-time convolver chip that exhibits several new features, including a multikernel mode.

AB - The model used for architectural optimization is discussed. It is then shown that the optimal architecture for 2-D convolution uses a 1-D convolution combinatorial operator to reduce the 2-D problem to a classical 1-D systolic array. Furthermore, for a given technology and chip area, if one tries to apply the proposed cost function to this architecture, it is possible to predict a practical bound for the kernel size of convolutions that can be implemented on one chip. Details are given of a 5 × 10 real-time convolver chip that exhibits several new features, including a multikernel mode.

M3 - Conference article

AN - SCOPUS:0025643645

SN - 0886-5930

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90

Y2 - 13 May 1990 through 16 May 1990

ER -

A real-time multi-kernel picture convolver

Abstract

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