A reconfigurable design-for-debug infrastructure for SoCs

Miron Abramovici; Paul Bradley; Kumar Dwarakanath; Peter Levin; Gerard Memmi; Dave Miller

doi:10.1145/1146909.1146916

A reconfigurable design-for-debug infrastructure for SoCs

Miron Abramovici, Paul Bradley, Kumar Dwarakanath, Peter Levin, Gerard Memmi, Dave Miller

Inc.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.

Original language	English
Title of host publication	2006 43rd ACM/IEEE Design Automation Conference, DAC'06
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	7-12
Number of pages	6
ISBN (Print)	1595933816, 1595933816, 9781595933812
DOIs	https://doi.org/10.1145/1146909.1146916
Publication status	Published - 1 Jan 2006
Externally published	Yes
Event	43rd Annual Design Automation Conference, DAC 2006 - San Francisco, CA, United States Duration: 24 Jul 2006 → 28 Jul 2006

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	43rd Annual Design Automation Conference, DAC 2006
Country/Territory	United States
City	San Francisco, CA
Period	24/07/06 → 28/07/06

Keywords

Assertion-based debug
At-speed debug
Silicon debug
What-if experiments

Access to Document

10.1145/1146909.1146916

Cite this

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title = "A reconfigurable design-for-debug infrastructure for SoCs",

abstract = "In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.",

keywords = "Assertion-based debug, At-speed debug, Silicon debug, What-if experiments",

author = "Miron Abramovici and Paul Bradley and Kumar Dwarakanath and Peter Levin and Gerard Memmi and Dave Miller",

year = "2006",

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doi = "10.1145/1146909.1146916",

language = "English",

isbn = "1595933816",

series = "Proceedings - Design Automation Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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note = "43rd Annual Design Automation Conference, DAC 2006 ; Conference date: 24-07-2006 Through 28-07-2006",

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Abramovici, M, Bradley, P, Dwarakanath, K, Levin, P, Memmi, G & Miller, D 2006, A reconfigurable design-for-debug infrastructure for SoCs. in 2006 43rd ACM/IEEE Design Automation Conference, DAC'06. Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., pp. 7-12, 43rd Annual Design Automation Conference, DAC 2006, San Francisco, CA, United States, 24/07/06. https://doi.org/10.1145/1146909.1146916

A reconfigurable design-for-debug infrastructure for SoCs. / Abramovici, Miron; Bradley, Paul; Dwarakanath, Kumar et al.
2006 43rd ACM/IEEE Design Automation Conference, DAC'06. Institute of Electrical and Electronics Engineers Inc., 2006. p. 7-12 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A reconfigurable design-for-debug infrastructure for SoCs

AU - Abramovici, Miron

AU - Bradley, Paul

AU - Dwarakanath, Kumar

AU - Levin, Peter

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AU - Miller, Dave

PY - 2006/1/1

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N2 - In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.

AB - In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.

KW - Assertion-based debug

KW - At-speed debug

KW - Silicon debug

KW - What-if experiments

U2 - 10.1145/1146909.1146916

DO - 10.1145/1146909.1146916

M3 - Conference contribution

AN - SCOPUS:34547229372

SN - 1595933816

SN - 9781595933812

T3 - Proceedings - Design Automation Conference

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BT - 2006 43rd ACM/IEEE Design Automation Conference, DAC'06

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 43rd Annual Design Automation Conference, DAC 2006

Y2 - 24 July 2006 through 28 July 2006

ER -

A reconfigurable design-for-debug infrastructure for SoCs

Abstract

Publication series

Conference

Keywords

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