A SOPC oriented FPGA implementation of JPEG-2000 entropy coder

Aouadi; O. Hammami

A SOPC oriented FPGA implementation of JPEG-2000 entropy coder

Aouadi
, O. Hammami

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An overview is given of the implementation of the entropy coder on programmable circuits FPGA Xilinx Virtex-II. The implementation runs at 71 Mhz for about 220,000 equivalent system gates which place the circuit in the reach of a Virtex II XV250-6-CS144 chip or a 2VP250 Pro. This approach is more general and cost effective than existing proposed products for JPEG-2000 coders since the chip keeps full multiprocessing capabilities for other processing while still having its dedicated logic free to be dynamically reconfigured to serve for other computationally intensive processing.

Original language	English
Title of host publication	Picture Coding Symposium
Pages	327-328
Number of pages	2
Publication status	Published - 9 Dec 2003
Event	Picture Coding Symposium - Saint Malo, France Duration: 23 Apr 2003 → 25 Apr 2003

Publication series

Name	Picture Coding Symposium

Conference

Conference	Picture Coding Symposium
Country/Territory	France
City	Saint Malo
Period	23/04/03 → 25/04/03

Cite this

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title = "A SOPC oriented FPGA implementation of JPEG-2000 entropy coder",

abstract = "An overview is given of the implementation of the entropy coder on programmable circuits FPGA Xilinx Virtex-II. The implementation runs at 71 Mhz for about 220,000 equivalent system gates which place the circuit in the reach of a Virtex II XV250-6-CS144 chip or a 2VP250 Pro. This approach is more general and cost effective than existing proposed products for JPEG-2000 coders since the chip keeps full multiprocessing capabilities for other processing while still having its dedicated logic free to be dynamically reconfigured to serve for other computationally intensive processing.",

author = "Aouadi and O. Hammami",

year = "2003",

month = dec,

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AU - Hammami, O.

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N2 - An overview is given of the implementation of the entropy coder on programmable circuits FPGA Xilinx Virtex-II. The implementation runs at 71 Mhz for about 220,000 equivalent system gates which place the circuit in the reach of a Virtex II XV250-6-CS144 chip or a 2VP250 Pro. This approach is more general and cost effective than existing proposed products for JPEG-2000 coders since the chip keeps full multiprocessing capabilities for other processing while still having its dedicated logic free to be dynamically reconfigured to serve for other computationally intensive processing.

AB - An overview is given of the implementation of the entropy coder on programmable circuits FPGA Xilinx Virtex-II. The implementation runs at 71 Mhz for about 220,000 equivalent system gates which place the circuit in the reach of a Virtex II XV250-6-CS144 chip or a 2VP250 Pro. This approach is more general and cost effective than existing proposed products for JPEG-2000 coders since the chip keeps full multiprocessing capabilities for other processing while still having its dedicated logic free to be dynamically reconfigured to serve for other computationally intensive processing.

UR - https://www.scopus.com/pages/publications/0344035567

M3 - Conference contribution

AN - SCOPUS:0344035567

SN - 2726112420

T3 - Picture Coding Symposium

SP - 327

EP - 328

BT - Picture Coding Symposium

T2 - Picture Coding Symposium

Y2 - 23 April 2003 through 25 April 2003

ER -

A SOPC oriented FPGA implementation of JPEG-2000 entropy coder

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