TY - GEN
T1 - A statically scheduled time-division-multiplexed network-on-chip for real-time systems
AU - Schoeberl, Martin
AU - Brandner, Florian
AU - Sparsø, Jens
AU - Kasapaki, Evangelia
PY - 2012/6/29
Y1 - 2012/6/29
N2 - This paper explores the design of a circuit-switched network-on-chip (NoC) based on time-division-multiplexing (TDM) for use in hard real-time systems. Previous work has primarily considered application-specific systems. The work presented here targets general-purpose hardware platforms. We consider a system with IP-cores, where the TDM-NoC must provide directed virtual circuits - all with the same bandwidth - between all nodes. This may not be a frequent scenario, but a general platform should provide this capability, and it is an interesting point in the design space to study. The paper presents an FPGA-friendly hardware design, which is simple, fast, and consumes minimal resources. Furthermore, an algorithm to find minimum-period schedules for all-to-all virtual circuits on top of typical physical NoC topologies like 2D-mesh, torus, bidirectional torus, tree, and fat-tree is presented. The static schedule makes the NoC time-predictable and enables worst-case execution time analysis of communicating real-time tasks.
AB - This paper explores the design of a circuit-switched network-on-chip (NoC) based on time-division-multiplexing (TDM) for use in hard real-time systems. Previous work has primarily considered application-specific systems. The work presented here targets general-purpose hardware platforms. We consider a system with IP-cores, where the TDM-NoC must provide directed virtual circuits - all with the same bandwidth - between all nodes. This may not be a frequent scenario, but a general platform should provide this capability, and it is an interesting point in the design space to study. The paper presents an FPGA-friendly hardware design, which is simple, fast, and consumes minimal resources. Furthermore, an algorithm to find minimum-period schedules for all-to-all virtual circuits on top of typical physical NoC topologies like 2D-mesh, torus, bidirectional torus, tree, and fat-tree is presented. The static schedule makes the NoC time-predictable and enables worst-case execution time analysis of communicating real-time tasks.
KW - network-on-chip
KW - real-time systems
U2 - 10.1109/NOCS.2012.25
DO - 10.1109/NOCS.2012.25
M3 - Conference contribution
AN - SCOPUS:84862743992
SN - 9780769546773
T3 - Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012
SP - 152
EP - 160
BT - Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012
T2 - 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012
Y2 - 9 May 2012 through 11 May 2012
ER -