A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection Models

Roukoz Nabhan, Jean Max Dutertre, Jean Baptiste Rigaud, Jean Luc Danger, Laurent Sauvage

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Investigating the dynamics and mechanisms of Electromagnetic Fault Injection (EMFI) attacks, which expose an active circuit to electromagnetic disturbances, presents a persisting challenge due to the diverse and complex fault mechanisms involved. An improved understanding of EMFI modeling is paramount for developing proficient on-chip detection sensors, serving as countermeasures to these attacks. In light of this, our research evaluated the effectiveness of EMFI detection sensors, introduced by Elbaze et al., which rest on the premise that the sampling fault model accounts for EMFI. To assess the functionality of these sensors, we integrated them into an Advanced Encryption Standard (AES) accelerator of a Field-Programmable Gate Array (FPGA) and performed a series of experiments. The resulting evidence suggests that the explanation for EMFI is not a singular fault model but rather, two underlying mechanisms are implicated. At high frequencies, which corresponds to low slack, electromagnetic disturbances, in tandem with the target's Power Distribution Network (PDN), initiated timing constraint violations. This violation subsequently increased the logic propagation times, surpassing the clock period. Contrarily, at low to moderate frequencies, the induced faults generally aligned with the sampling fault model. However, certain deviations from the theoretical framework called into question the model's validity. Upon a deeper examination of the results, we determined that these faults, rather than being sampling faults, were tied to a different mechanism. Electromagnetic disturbances, when coupled with a target's Clock Distribution Network (CDN), can cause timing constraint violations due to EMFI-induced voltage glitches within the target's clock tree. By integrating the mechanisms of EMFI-induced clock glitches and timing faults into the timing violations fault model, we attain a holistic comprehension of EMFI mechanisms. It encapsulates both mechanisms induced by EMFI, spanning the full-frequency spectrum of the target.

Original languageEnglish
Title of host publicationProceedings - 2023 Workshop on Fault Detection and Tolerance in Cryptography, FDTC 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-12
Number of pages12
ISBN (Electronic)9798350342529
DOIs
Publication statusPublished - 1 Jan 2023
Externally publishedYes
Event20th Workshop on Fault Detection and Tolerance in Cryptography, FDTC 2023 - Prague, Czech Republic
Duration: 10 Sept 2023 → …

Publication series

NameProceedings - 2023 Workshop on Fault Detection and Tolerance in Cryptography, FDTC 2023

Conference

Conference20th Workshop on Fault Detection and Tolerance in Cryptography, FDTC 2023
Country/TerritoryCzech Republic
CityPrague
Period10/09/23 → …

Keywords

  • EMFI
  • EMFI-induced clock glitches
  • fully digital sensor
  • sampling fault model
  • timing faults
  • timing violations fault model

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