A tool for transient fault analysis in combinational circuits

Mariem Slimani, Lirida Naviner

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

With technology downscaling, the vulnerability of combinational logic circuits to transient faults has increased resulting in error rates approaching those of memories. Thus, to guarantee a good use of selective hardening techniques, fast and accurate approaches for transient fault analysis in logic circuits are needed. In this work, we describe a methodology for Soft Error Rate (SER) evaluation in combinational logic circuits that manages the dependency of logical and electrical masking effects in case of reconvergent fanouts. The approach combines analytical transient fault propagation model and fault simulation to speed up simulations.

Original languageEnglish
Title of host publication2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages125-128
Number of pages4
ISBN (Electronic)9781509002467
DOIs
Publication statusPublished - 23 Mar 2016
Externally publishedYes
EventIEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015 - Cairo, Egypt
Duration: 6 Dec 20159 Dec 2015

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume2016-March

Conference

ConferenceIEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015
Country/TerritoryEgypt
CityCairo
Period6/12/159/12/15

Keywords

  • Transient faults
  • logic circuits
  • masking effects
  • reconvergent fanouts

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