A variation-adaptive retiming method exploiting reconfigurability

Zhenyu Guan; Justin S.J. Wong; Sumanta Chaudhuri; George Constantinides; Peter Y.K. Cheung

doi:10.1109/FPL.2013.6645577

A variation-adaptive retiming method exploiting reconfigurability

Zhenyu Guan, Justin S.J. Wong, Sumanta Chaudhuri, George Constantinides, Peter Y.K. Cheung

Imperial College London

Research output: Contribution to conference › Paper › peer-review

Abstract

In this article we present a variation-aware post placement and routing (P&R) retiming method to counteract process variation in FPGAs. Variation-aware retiming takes into account exact variation maps (measured on FPGAs) as opposed to statistical static timing analysis (SSTA) which models process variation with statistical distributions. Experiments are conducted using variation maps measured from 100 Cyclone III FPGAs, and the retiming algorithm is applied using MATLAB. We have shown that for circuits with several retiming choices of equivalent logic depth, up to 30% delay improvement can be achieved for a given variation coefficient of σ/μ = 0.3.

Original language	English
DOIs	https://doi.org/10.1109/FPL.2013.6645577
Publication status	Published - 1 Jan 2013
Externally published	Yes
Event	2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Porto, Portugal Duration: 2 Sept 2013 → 4 Sept 2013

Conference

Conference	2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013
Country/Territory	Portugal
City	Porto
Period	2/09/13 → 4/09/13

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10.1109/FPL.2013.6645577

Cite this

@conference{ebae656a65c940779ab0958487c6e5a9,

title = "A variation-adaptive retiming method exploiting reconfigurability",

abstract = "In this article we present a variation-aware post placement and routing (P\&R) retiming method to counteract process variation in FPGAs. Variation-aware retiming takes into account exact variation maps (measured on FPGAs) as opposed to statistical static timing analysis (SSTA) which models process variation with statistical distributions. Experiments are conducted using variation maps measured from 100 Cyclone III FPGAs, and the retiming algorithm is applied using MATLAB. We have shown that for circuits with several retiming choices of equivalent logic depth, up to 30\% delay improvement can be achieved for a given variation coefficient of σ/μ = 0.3.",

author = "Zhenyu Guan and Wong, \{Justin S.J.\} and Sumanta Chaudhuri and George Constantinides and Cheung, \{Peter Y.K.\}",

year = "2013",

month = jan,

day = "1",

doi = "10.1109/FPL.2013.6645577",

language = "English",

note = "2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 ; Conference date: 02-09-2013 Through 04-09-2013",

}

TY - CONF

T1 - A variation-adaptive retiming method exploiting reconfigurability

AU - Guan, Zhenyu

AU - Wong, Justin S.J.

AU - Chaudhuri, Sumanta

AU - Constantinides, George

AU - Cheung, Peter Y.K.

PY - 2013/1/1

Y1 - 2013/1/1

N2 - In this article we present a variation-aware post placement and routing (P&R) retiming method to counteract process variation in FPGAs. Variation-aware retiming takes into account exact variation maps (measured on FPGAs) as opposed to statistical static timing analysis (SSTA) which models process variation with statistical distributions. Experiments are conducted using variation maps measured from 100 Cyclone III FPGAs, and the retiming algorithm is applied using MATLAB. We have shown that for circuits with several retiming choices of equivalent logic depth, up to 30% delay improvement can be achieved for a given variation coefficient of σ/μ = 0.3.

AB - In this article we present a variation-aware post placement and routing (P&R) retiming method to counteract process variation in FPGAs. Variation-aware retiming takes into account exact variation maps (measured on FPGAs) as opposed to statistical static timing analysis (SSTA) which models process variation with statistical distributions. Experiments are conducted using variation maps measured from 100 Cyclone III FPGAs, and the retiming algorithm is applied using MATLAB. We have shown that for circuits with several retiming choices of equivalent logic depth, up to 30% delay improvement can be achieved for a given variation coefficient of σ/μ = 0.3.

U2 - 10.1109/FPL.2013.6645577

DO - 10.1109/FPL.2013.6645577

M3 - Paper

AN - SCOPUS:84898636360

T2 - 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013

Y2 - 2 September 2013 through 4 September 2013

ER -

A variation-adaptive retiming method exploiting reconfigurability

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