Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration

Hao Cai; You Wang; Lirida Alves De Barros Naviner; Xinning Liu; Weiwei Shan; Jun Yang; Weisheng Zhao

doi:10.1109/TCSI.2018.2854277

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration

Hao Cai, You Wang, Lirida Alves De Barros Naviner, Xinning Liu, Weiwei Shan, Jun Yang, Weisheng Zhao

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, we discuss the potential foundry announced integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FDSOI). The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next-generation voltage-controlled magnetic anisotropy MTJ are separately integrated into a 28-nm FDSOI process as the MRAM or magnetoelectric random access memory (MeRAM)-on-FDSOI integration. Micromagnetic and electrical simulations are used to evaluate the performance of hybrid circuits. Circuit-level design strategies are explored that use FDSOI leverage and spin-device characteristic to realize writing and sensing power-delay efficiency, robust, and reliable performance in the one-Transistor one-MTJ MRAM/MeRAM bit-cell and sensing circuits. Reliability issues are discussed. Process variation and aging resilience strategies, e.g., step-wise back-bias, flip-well re-configuration, and write assist, are proposed to address failure and aging degradation in the MRAM/MeRAM-on-FDSOI integration. A qualitative summary demonstrates that the MRAM/MeRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.

Original language	English
Article number	8439066
Pages (from-to)	239-250
Number of pages	12
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	66
Issue number	1
DOIs	https://doi.org/10.1109/TCSI.2018.2854277
Publication status	Published - 1 Jan 2019
Externally published	Yes

Keywords

Fully depleted silicon-on-insulator (FDSOI)
aging
magnetic tunnel junction (MTJ)
magnetoelectric random access memory (MeRAM)
reliability
spin transfer torque magnetic random access memory (STT-MRAM)
variability
voltage-controlled magnetic anisotropy (VCMA)

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10.1109/TCSI.2018.2854277

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title = "Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration",

abstract = "In this paper, we discuss the potential foundry announced integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FDSOI). The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next-generation voltage-controlled magnetic anisotropy MTJ are separately integrated into a 28-nm FDSOI process as the MRAM or magnetoelectric random access memory (MeRAM)-on-FDSOI integration. Micromagnetic and electrical simulations are used to evaluate the performance of hybrid circuits. Circuit-level design strategies are explored that use FDSOI leverage and spin-device characteristic to realize writing and sensing power-delay efficiency, robust, and reliable performance in the one-Transistor one-MTJ MRAM/MeRAM bit-cell and sensing circuits. Reliability issues are discussed. Process variation and aging resilience strategies, e.g., step-wise back-bias, flip-well re-configuration, and write assist, are proposed to address failure and aging degradation in the MRAM/MeRAM-on-FDSOI integration. A qualitative summary demonstrates that the MRAM/MeRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.",

keywords = "Fully depleted silicon-on-insulator (FDSOI), aging, magnetic tunnel junction (MTJ), magnetoelectric random access memory (MeRAM), reliability, spin transfer torque magnetic random access memory (STT-MRAM), variability, voltage-controlled magnetic anisotropy (VCMA)",

author = "Hao Cai and You Wang and \{De Barros Naviner\}, \{Lirida Alves\} and Xinning Liu and Weiwei Shan and Jun Yang and Weisheng Zhao",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2019",

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doi = "10.1109/TCSI.2018.2854277",

language = "English",

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T1 - Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration

AU - Cai, Hao

AU - Wang, You

AU - De Barros Naviner, Lirida Alves

AU - Liu, Xinning

AU - Shan, Weiwei

AU - Yang, Jun

AU - Zhao, Weisheng

PY - 2019/1/1

Y1 - 2019/1/1

N2 - In this paper, we discuss the potential foundry announced integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FDSOI). The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next-generation voltage-controlled magnetic anisotropy MTJ are separately integrated into a 28-nm FDSOI process as the MRAM or magnetoelectric random access memory (MeRAM)-on-FDSOI integration. Micromagnetic and electrical simulations are used to evaluate the performance of hybrid circuits. Circuit-level design strategies are explored that use FDSOI leverage and spin-device characteristic to realize writing and sensing power-delay efficiency, robust, and reliable performance in the one-Transistor one-MTJ MRAM/MeRAM bit-cell and sensing circuits. Reliability issues are discussed. Process variation and aging resilience strategies, e.g., step-wise back-bias, flip-well re-configuration, and write assist, are proposed to address failure and aging degradation in the MRAM/MeRAM-on-FDSOI integration. A qualitative summary demonstrates that the MRAM/MeRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.

AB - In this paper, we discuss the potential foundry announced integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FDSOI). The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next-generation voltage-controlled magnetic anisotropy MTJ are separately integrated into a 28-nm FDSOI process as the MRAM or magnetoelectric random access memory (MeRAM)-on-FDSOI integration. Micromagnetic and electrical simulations are used to evaluate the performance of hybrid circuits. Circuit-level design strategies are explored that use FDSOI leverage and spin-device characteristic to realize writing and sensing power-delay efficiency, robust, and reliable performance in the one-Transistor one-MTJ MRAM/MeRAM bit-cell and sensing circuits. Reliability issues are discussed. Process variation and aging resilience strategies, e.g., step-wise back-bias, flip-well re-configuration, and write assist, are proposed to address failure and aging degradation in the MRAM/MeRAM-on-FDSOI integration. A qualitative summary demonstrates that the MRAM/MeRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.

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KW - aging

KW - magnetic tunnel junction (MTJ)

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KW - reliability

KW - spin transfer torque magnetic random access memory (STT-MRAM)

KW - variability

KW - voltage-controlled magnetic anisotropy (VCMA)

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DO - 10.1109/TCSI.2018.2854277

M3 - Article

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VL - 66

SP - 239

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JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 1

M1 - 8439066

ER -

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration

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