An 8x8 run-time reconfigurable FPGA embedded in a SoC

Sumanta Chaudhuri; Sylvain Guilley; Florent Flament; Philippe Hoogvorst; Jean Luc Danger

doi:10.1109/DAC.2008.4555793

An 8x8 run-time reconfigurable FPGA embedded in a SoC

Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean Luc Danger

CNRS LTCI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionality free of electrical conflicts, and we present a flow based on Altera synthesis tools to implement IPs(Hardware Blocks) in this FPGA. We demonstrate the full functionality with experiments on the FPGA, and as conclusion we highlight the limitations and future research directions.

Original language	English
Title of host publication	Proceedings of the 45th Design Automation Conference, DAC
Pages	120-125
Number of pages	6
DOIs	https://doi.org/10.1109/DAC.2008.4555793
Publication status	Published - 17 Sept 2008
Externally published	Yes
Event	45th Design Automation Conference, DAC - Anaheim, CA, United States Duration: 8 Jun 2008 → 13 Jun 2008

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	45th Design Automation Conference, DAC
Country/Territory	United States
City	Anaheim, CA
Period	8/06/08 → 13/06/08

Keywords

FPGA
RTR

Access to Document

10.1109/DAC.2008.4555793

Cite this

@inproceedings{c5a1bb007f8c40559c0cba99077a7c5c,

title = "An 8x8 run-time reconfigurable FPGA embedded in a SoC",

abstract = "This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionality free of electrical conflicts, and we present a flow based on Altera synthesis tools to implement IPs(Hardware Blocks) in this FPGA. We demonstrate the full functionality with experiments on the FPGA, and as conclusion we highlight the limitations and future research directions.",

keywords = "FPGA, RTR",

author = "Sumanta Chaudhuri and Sylvain Guilley and Florent Flament and Philippe Hoogvorst and Danger, \{Jean Luc\}",

year = "2008",

month = sep,

day = "17",

doi = "10.1109/DAC.2008.4555793",

language = "English",

isbn = "9781605581156",

series = "Proceedings - Design Automation Conference",

pages = "120--125",

booktitle = "Proceedings of the 45th Design Automation Conference, DAC",

note = "45th Design Automation Conference, DAC ; Conference date: 08-06-2008 Through 13-06-2008",

}

Chaudhuri, S, Guilley, S, Flament, F, Hoogvorst, P & Danger, JL 2008, An 8x8 run-time reconfigurable FPGA embedded in a SoC. in Proceedings of the 45th Design Automation Conference, DAC., 4555793, Proceedings - Design Automation Conference, pp. 120-125, 45th Design Automation Conference, DAC, Anaheim, CA, United States, 8/06/08. https://doi.org/10.1109/DAC.2008.4555793

TY - GEN

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AU - Chaudhuri, Sumanta

AU - Guilley, Sylvain

AU - Flament, Florent

AU - Hoogvorst, Philippe

AU - Danger, Jean Luc

PY - 2008/9/17

Y1 - 2008/9/17

N2 - This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionality free of electrical conflicts, and we present a flow based on Altera synthesis tools to implement IPs(Hardware Blocks) in this FPGA. We demonstrate the full functionality with experiments on the FPGA, and as conclusion we highlight the limitations and future research directions.

AB - This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionality free of electrical conflicts, and we present a flow based on Altera synthesis tools to implement IPs(Hardware Blocks) in this FPGA. We demonstrate the full functionality with experiments on the FPGA, and as conclusion we highlight the limitations and future research directions.

KW - FPGA

KW - RTR

U2 - 10.1109/DAC.2008.4555793

DO - 10.1109/DAC.2008.4555793

M3 - Conference contribution

AN - SCOPUS:51549102261

SN - 9781605581156

T3 - Proceedings - Design Automation Conference

SP - 120

EP - 125

BT - Proceedings of the 45th Design Automation Conference, DAC

T2 - 45th Design Automation Conference, DAC

Y2 - 8 June 2008 through 13 June 2008

ER -

An 8x8 run-time reconfigurable FPGA embedded in a SoC

Abstract

Publication series

Conference

Keywords

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