An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities

Josep Torras Flaquer; Jean Marc Daveau; Lirida Naviner; Philippe Roche

doi:10.1109/IOLTS.2011.5993818

An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities

Josep Torras Flaquer
, Jean Marc Daveau
, Lirida Naviner
, Philippe Roche

STMicroelectronics SA, France
Telecom Paris

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Citations (Scopus)

Abstract

We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of combinatorial logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.

Original language	English
Title of host publication	Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011
Pages	98-103
Number of pages	6
DOIs	https://doi.org/10.1109/IOLTS.2011.5993818
Publication status	Published - 19 Sept 2011
Event	2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 - Athens, Greece Duration: 13 Jul 2011 → 15 Jul 2011

Publication series

Name	Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011

Conference

Conference	2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011
Country/Territory	Greece
City	Athens
Period	13/07/11 → 15/07/11

Keywords

SER
SET
circuit clustering
circuit reliability
logic design
probability
reliability estimation

Access to Document

10.1109/IOLTS.2011.5993818

Cite this

Flaquer, J. T., Daveau, J. M., Naviner, L., & Roche, P. (2011). An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. In Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 (pp. 98-103). Article 5993818 (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011). https://doi.org/10.1109/IOLTS.2011.5993818

Flaquer, Josep Torras ; Daveau, Jean Marc ; Naviner, Lirida et al. / An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. 2011. pp. 98-103 (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011).

@inproceedings{b2a5c687a86341159aae3aca0e7afbfa,

title = "An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities",

abstract = "We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of combinatorial logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.",

keywords = "SER, SET, circuit clustering, circuit reliability, logic design, probability, reliability estimation",

author = "Flaquer, \{Josep Torras\} and Daveau, \{Jean Marc\} and Lirida Naviner and Philippe Roche",

year = "2011",

month = sep,

day = "19",

doi = "10.1109/IOLTS.2011.5993818",

language = "English",

isbn = "9781457710551",

series = "Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011",

pages = "98--103",

booktitle = "Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011",

note = "2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011 ; Conference date: 13-07-2011 Through 15-07-2011",

}

Flaquer, JT, Daveau, JM, Naviner, L & Roche, P 2011, An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. in Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011., 5993818, Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011, pp. 98-103, 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011, Athens, Greece, 13/07/11. https://doi.org/10.1109/IOLTS.2011.5993818

An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. / Flaquer, Josep Torras; Daveau, Jean Marc; Naviner, Lirida et al.
Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. 2011. p. 98-103 5993818 (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Naviner, Lirida

AU - Roche, Philippe

PY - 2011/9/19

Y1 - 2011/9/19

N2 - We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of combinatorial logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.

AB - We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of combinatorial logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.

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KW - SET

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KW - circuit reliability

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KW - probability

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DO - 10.1109/IOLTS.2011.5993818

M3 - Conference contribution

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T3 - Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011

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T2 - 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011

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Flaquer JT, Daveau JM, Naviner L, Roche P. An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. In Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011. 2011. p. 98-103. 5993818. (Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011). doi: 10.1109/IOLTS.2011.5993818

An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities

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