An iterative reconfigurability approach for WCDMA high-data-rate communications

Reconfigurability is a multidimensional concept, and its algorithmic and hardware expressions are formalized in a two-layer structure. The interplay between the two reconfigurability layers categorizes the different approaches in the literature. In this article we introduce a novel reconfigurability approach called iterative reconfigurability. This approach combines the two reconfigurability layers by supposing algorithms with computational similarities and iterativeness. Based on the computational overlaps and the possibility to iteratively perform the required computations of the supporting algorithms, this approach corresponds to a simple hardware core. This core implements only a single computation (one iteration) of each algorithm and can be used in an iterative/serial fashion. Switching between the different essential computations is performed without complicated architectural changes due to the high degree of computational overlaps. The iterative approach introduces a new system parameter: the maximum number of available iterations. This parameter is appropriately divided among the different algorithms in order to optimize system performance. The iterative approach minimizes the used hardware area and the reconfiguration logic, and thus is appropriate for critical implementation constraints as in user mobile terminals. A complete example of a reconfigurable WCDMA receiver for high data rates is presented and analyzed. This receiver is based on the computational similarities and iterative nature of two main functions: RAKE demodulation and interference cancellation. This case demonstrates the value of the iterative reconfigurability approach.