An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS

Paul Chollet; Benoit Larras; Cyril Lahuec; Fabrice Seguin; Matthieu Arzel

doi:10.1109/NEWCAS.2017.8010091

An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS

Paul Chollet
, Benoit Larras
, Cyril Lahuec
, Fabrice Seguin
, Matthieu Arzel

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Clique-based neural networks are less complex than commonly used neural network models. They have a limited connectivity and are composed of simple functions. They are thus adapted to implement neuro-inspired computation units operating under severe energy constraints. This paper shows an ST 65-nm CMOS ASIC implementation for a 30-neuron clique-based neural network circuit. With a 1V power supply and 300nA unitary current, the neuron energy consumption is only 17fJ per synaptic event. The network occupies a 41,820μm² silicon area.

Original language	English
Title of host publication	Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	5-8
Number of pages	4
ISBN (Electronic)	9781509049905
DOIs	https://doi.org/10.1109/NEWCAS.2017.8010091
Publication status	Published - 11 Aug 2017
Externally published	Yes
Event	15th IEEE International New Circuits and Systems Conference, NEWCAS 2017 - Strasbourg, France Duration: 25 Jun 2017 → 28 Jun 2017

Publication series

Name	Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017

Conference

Conference	15th IEEE International New Circuits and Systems Conference, NEWCAS 2017
Country/Territory	France
City	Strasbourg
Period	25/06/17 → 28/06/17

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Access to Document

10.1109/NEWCAS.2017.8010091

Cite this

Chollet, P., Larras, B., Lahuec, C., Seguin, F., & Arzel, M. (2017). An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS. In Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017 (pp. 5-8). Article 8010091 (Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NEWCAS.2017.8010091

Chollet, Paul ; Larras, Benoit ; Lahuec, Cyril et al. / An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS. Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 5-8 (Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017).

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title = "An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS",

abstract = "Clique-based neural networks are less complex than commonly used neural network models. They have a limited connectivity and are composed of simple functions. They are thus adapted to implement neuro-inspired computation units operating under severe energy constraints. This paper shows an ST 65-nm CMOS ASIC implementation for a 30-neuron clique-based neural network circuit. With a 1V power supply and 300nA unitary current, the neuron energy consumption is only 17fJ per synaptic event. The network occupies a 41,820μm2 silicon area.",

author = "Paul Chollet and Benoit Larras and Cyril Lahuec and Fabrice Seguin and Matthieu Arzel",

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year = "2017",

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doi = "10.1109/NEWCAS.2017.8010091",

language = "English",

series = "Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017",

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Chollet, P, Larras, B, Lahuec, C, Seguin, F & Arzel, M 2017, An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS. in Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017., 8010091, Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017, Institute of Electrical and Electronics Engineers Inc., pp. 5-8, 15th IEEE International New Circuits and Systems Conference, NEWCAS 2017, Strasbourg, France, 25/06/17. https://doi.org/10.1109/NEWCAS.2017.8010091

An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS. / Chollet, Paul; Larras, Benoit; Lahuec, Cyril et al.
Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 5-8 8010091 (Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS

AU - Chollet, Paul

AU - Larras, Benoit

AU - Lahuec, Cyril

AU - Seguin, Fabrice

AU - Arzel, Matthieu

PY - 2017/8/11

Y1 - 2017/8/11

N2 - Clique-based neural networks are less complex than commonly used neural network models. They have a limited connectivity and are composed of simple functions. They are thus adapted to implement neuro-inspired computation units operating under severe energy constraints. This paper shows an ST 65-nm CMOS ASIC implementation for a 30-neuron clique-based neural network circuit. With a 1V power supply and 300nA unitary current, the neuron energy consumption is only 17fJ per synaptic event. The network occupies a 41,820μm2 silicon area.

AB - Clique-based neural networks are less complex than commonly used neural network models. They have a limited connectivity and are composed of simple functions. They are thus adapted to implement neuro-inspired computation units operating under severe energy constraints. This paper shows an ST 65-nm CMOS ASIC implementation for a 30-neuron clique-based neural network circuit. With a 1V power supply and 300nA unitary current, the neuron energy consumption is only 17fJ per synaptic event. The network occupies a 41,820μm2 silicon area.

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U2 - 10.1109/NEWCAS.2017.8010091

DO - 10.1109/NEWCAS.2017.8010091

M3 - Conference contribution

AN - SCOPUS:85034450544

T3 - Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017

SP - 5

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BT - Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 15th IEEE International New Circuits and Systems Conference, NEWCAS 2017

Y2 - 25 June 2017 through 28 June 2017

ER -

Chollet P, Larras B, Lahuec C, Seguin F, Arzel M. An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS. In Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 5-8. 8010091. (Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017). doi: 10.1109/NEWCAS.2017.8010091

An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS

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