Analog Duty Cycle Controller Using Backgate Body Biasing for 5G Millimeter Wave Applications

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Abstract

This work presents the first 21 - 43 GHz CMOS analog Duty Cycle Controller (DCC) implemented in 28 nm FDSOI. The main application is millimeter wave mixers with CMOS digital signals. The proposed circuit corrects the input duty cycle with a negative feedback analog loop. Observability of the duty cycle is made through a passive low pass filter and the control is achieved by modifying the rise and fall time of the input clock signal, via backgate biasing of an inverter chain. The circuit has been validated by post layout, Monte-Carlo and corner simulations. At 28 GHz, the duty cycle correction range varies from 40 % to 55 %, and the additional power consumption introduced by the correction loop is frequency independent and is equal to 0.6mW.

Original languageEnglish
Title of host publication2021 28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728182810
DOIs
Publication statusPublished - 1 Jan 2021
Event28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021 - Dubai, United Arab Emirates
Duration: 28 Nov 20211 Dec 2021

Publication series

Name2021 28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021 - Proceedings

Conference

Conference28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021
Country/TerritoryUnited Arab Emirates
CityDubai
Period28/11/211/12/21

Keywords

  • 28 nm FDSOI
  • Body Biasing
  • CMOS
  • Duty Cycle Controller
  • Millimeter Wave Frequency

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