Analyzing and alleviating the impact of errors on an SRAM-based FPGA cluster

Arwa Ben Dhia, Lirida Naviner, Philippe Matherat

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper proposes a method to analyze the effect of manufacturing defects and soft errors: stuck-ats and bit flips, on a cluster in a Mesh FPGA architecture. The cluster reliability is evaluated with a technique that is used in case of either a single error or multiple simultaneous faults. Simulation results show that the cluster is more robust to stuck-ats than to bit-flips, whatever the configuration memory is. Then, for selective hardening against bit flips, we propose an approach to identify the critical path and the most eligible component that is likely to improve the cluster reliability.

Original languageEnglish
Title of host publicationProceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012
Pages31-36
Number of pages6
DOIs
Publication statusPublished - 22 Nov 2012
Externally publishedYes
Event2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012 - Sitges, Spain
Duration: 27 Jun 201229 Jun 2012

Publication series

NameProceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012

Conference

Conference2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012
Country/TerritorySpain
CitySitges
Period27/06/1229/06/12

Keywords

  • Cluster
  • Crossbar
  • FPGA architecture
  • Interconnect
  • Look-up Table (LUT)
  • Rent parameter
  • SPR analysis
  • bit flip
  • eligibility
  • fault tolerance
  • selective hardening
  • stuck-at

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