Approche pour l'intégration du raffinement formel dans le processus de conception des SoCs

We present a methodology for proved communication refinement in system-level design space exploration of system-on-chip (SoC). The methodology we propose provides a formal approach for modeling and analysis the different levels of specification. Indeed, it provides a mean to build models of architecture and application at different levels of abstraction. It also allows us to verify formally the models at each level and to link the successive models by relation of refinement and to insure preservation of behavior.