TY - GEN
T1 - ARCHITECTURE FOR A DECODER OF ALGEBRAIC-GEOMETRIC CODES BASED ON HERMITIAN CURVES
AU - Lima, Leocarlos B.S.
AU - Naviner, Lirida A.B.
AU - Jaubert, Jocelyn
AU - Assis, Francisco M.
N1 - Publisher Copyright:
© 2003 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.
PY - 2003/1/1
Y1 - 2003/1/1
N2 - A new architecture is presented for hardware implementation of an algebraic-geometric code decoding algorithm based on a key equation criterion. This algorithm provides simultaneously error locator and evaluator polynomials. The architecture presented is suitable for hardware decoding of Hermitian codes.
AB - A new architecture is presented for hardware implementation of an algebraic-geometric code decoding algorithm based on a key equation criterion. This algorithm provides simultaneously error locator and evaluator polynomials. The architecture presented is suitable for hardware decoding of Hermitian codes.
UR - https://www.scopus.com/pages/publications/85150426384
U2 - 10.1109/MWSCAS.2003.1562576
DO - 10.1109/MWSCAS.2003.1562576
M3 - Conference contribution
AN - SCOPUS:85150426384
T3 - Midwest Symposium on Circuits and Systems
SP - 1482
EP - 1485
BT - Midwest Symposium on Circuits and Systems
A2 - Hamdy, Nadder
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003
Y2 - 27 December 2003 through 30 December 2003
ER -