Area/delay driven NoC synthesis

Abir M'zah; Omar Hammami

doi:10.1109/ICM.2011.6177364

Area/delay driven NoC synthesis

Abir M'zah
, Omar Hammami

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The NoC synthesis defined as the generation of a Network On Chip (NoC) architecture optimized for a specific application subject to various constraints, is a very important step in ASIC design methodologies. In this work we will present a new NoC synthesis method based on linear programming. We will apply our algorithm on multimedia coregraphs like 263 enc MP3 dec, MPEG4 and H.264. We reduce the complexity of the problem by restricting possible connections between cores having common destination or origin edges. The obtained results give a free NoC topology which satisfies the required bandwidth and the maximum propagation delay time with an optimized area of the NoC.

Original language	English
Title of host publication	2011 International Conference on Microelectronics, ICM 2011
DOIs	https://doi.org/10.1109/ICM.2011.6177364
Publication status	Published - 1 Dec 2011
Event	2011 23rd International Conference on Microelectronics, ICM 2011 - Hammamet, Tunisia Duration: 19 Dec 2011 → 22 Dec 2011

Publication series

Name	Proceedings of the International Conference on Microelectronics, ICM

Conference

Conference	2011 23rd International Conference on Microelectronics, ICM 2011
Country/Territory	Tunisia
City	Hammamet
Period	19/12/11 → 22/12/11

Keywords

Coregraph
Linear Programming
NoC synthesis
Optimization
complexity

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10.1109/ICM.2011.6177364

Cite this

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title = "Area/delay driven NoC synthesis",

abstract = "The NoC synthesis defined as the generation of a Network On Chip (NoC) architecture optimized for a specific application subject to various constraints, is a very important step in ASIC design methodologies. In this work we will present a new NoC synthesis method based on linear programming. We will apply our algorithm on multimedia coregraphs like 263 enc MP3 dec, MPEG4 and H.264. We reduce the complexity of the problem by restricting possible connections between cores having common destination or origin edges. The obtained results give a free NoC topology which satisfies the required bandwidth and the maximum propagation delay time with an optimized area of the NoC.",

keywords = "Coregraph, Linear Programming, NoC synthesis, Optimization, complexity",

author = "Abir M'zah and Omar Hammami",

year = "2011",

month = dec,

day = "1",

doi = "10.1109/ICM.2011.6177364",

language = "English",

isbn = "9781457722073",

series = "Proceedings of the International Conference on Microelectronics, ICM",

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note = "2011 23rd International Conference on Microelectronics, ICM 2011 ; Conference date: 19-12-2011 Through 22-12-2011",

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T1 - Area/delay driven NoC synthesis

AU - M'zah, Abir

AU - Hammami, Omar

PY - 2011/12/1

Y1 - 2011/12/1

N2 - The NoC synthesis defined as the generation of a Network On Chip (NoC) architecture optimized for a specific application subject to various constraints, is a very important step in ASIC design methodologies. In this work we will present a new NoC synthesis method based on linear programming. We will apply our algorithm on multimedia coregraphs like 263 enc MP3 dec, MPEG4 and H.264. We reduce the complexity of the problem by restricting possible connections between cores having common destination or origin edges. The obtained results give a free NoC topology which satisfies the required bandwidth and the maximum propagation delay time with an optimized area of the NoC.

AB - The NoC synthesis defined as the generation of a Network On Chip (NoC) architecture optimized for a specific application subject to various constraints, is a very important step in ASIC design methodologies. In this work we will present a new NoC synthesis method based on linear programming. We will apply our algorithm on multimedia coregraphs like 263 enc MP3 dec, MPEG4 and H.264. We reduce the complexity of the problem by restricting possible connections between cores having common destination or origin edges. The obtained results give a free NoC topology which satisfies the required bandwidth and the maximum propagation delay time with an optimized area of the NoC.

KW - Coregraph

KW - Linear Programming

KW - NoC synthesis

KW - Optimization

KW - complexity

UR - https://www.scopus.com/pages/publications/84860672644

U2 - 10.1109/ICM.2011.6177364

DO - 10.1109/ICM.2011.6177364

M3 - Conference contribution

AN - SCOPUS:84860672644

SN - 9781457722073

T3 - Proceedings of the International Conference on Microelectronics, ICM

BT - 2011 International Conference on Microelectronics, ICM 2011

T2 - 2011 23rd International Conference on Microelectronics, ICM 2011

Y2 - 19 December 2011 through 22 December 2011

ER -

Area/delay driven NoC synthesis

Abstract

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Keywords

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