TY - GEN
T1 - Assessing Security RISC
T2 - 22nd International Conference on Security and Cryptography, SECRYPT 2025
AU - Khan, Mahreen
AU - Mushtaq, Maria
AU - Pacalet, Renaud
AU - Apvrille, Ludovic
N1 - Publisher Copyright:
© 2025 by Paper published under CC license (CC BY-NC-ND 4.0).
PY - 2025/1/1
Y1 - 2025/1/1
N2 - Microarchitectural side-channel attacks exploit vulnerabilities such as cache behavior to leak sensitive data. These attacks have been extensively studied on x86 architectures but they remain less explored on RISC-V systems. A recent paper (Gerlach et al., 2023) demonstrated existing and novel microarchitectural attacks on RISC-V hardware platforms (C906, U74, C910, C908). This hardware-based analysis, while realistic, lacks the flexibility and detailed behavioral insights needed to fully understand these attacks. Simulation environments like gem5 (Lowe-Power, 2024) provide fine-grained control and diverse metrics to overcome this limitation and observe the attack in detail. In this paper, gem5 is used to explore Flush+Fault (Gerlach et al., 2023) side-channel attack on RISC-V architecture which was originally tested on RISC-V hardware. Through gem5, we analyze detailed insights of attack such as cache patterns, and timing behaviors. Our results demonstrate the gem5’s potential for advancing the understanding of RISC-V microarchitectural vulnerabilities and eventually for developing effective countermeasures.
AB - Microarchitectural side-channel attacks exploit vulnerabilities such as cache behavior to leak sensitive data. These attacks have been extensively studied on x86 architectures but they remain less explored on RISC-V systems. A recent paper (Gerlach et al., 2023) demonstrated existing and novel microarchitectural attacks on RISC-V hardware platforms (C906, U74, C910, C908). This hardware-based analysis, while realistic, lacks the flexibility and detailed behavioral insights needed to fully understand these attacks. Simulation environments like gem5 (Lowe-Power, 2024) provide fine-grained control and diverse metrics to overcome this limitation and observe the attack in detail. In this paper, gem5 is used to explore Flush+Fault (Gerlach et al., 2023) side-channel attack on RISC-V architecture which was originally tested on RISC-V hardware. Through gem5, we analyze detailed insights of attack such as cache patterns, and timing behaviors. Our results demonstrate the gem5’s potential for advancing the understanding of RISC-V microarchitectural vulnerabilities and eventually for developing effective countermeasures.
KW - Cache Timing Analysis
KW - Complex Systems
KW - Embedded Systems
KW - Microarchitectural Security
KW - Privacy
KW - RISC-V
KW - Security
KW - Side-Channel Attacks
KW - gem5 Simulator
UR - https://www.scopus.com/pages/publications/105010458282
U2 - 10.5220/0013518800003979
DO - 10.5220/0013518800003979
M3 - Conference contribution
AN - SCOPUS:105010458282
SN - 9789897587603
T3 - Proceedings of the International Conference on Security and Cryptography
SP - 607
EP - 612
BT - Proceedings of the 22nd International Conference on Security and Cryptography, SECRYPT 2025
A2 - De Capitani Di Vimercati, Sabrina
A2 - Samarati, Pierangela
PB - Science and Technology Publications, Lda
Y2 - 11 June 2025 through 13 June 2025
ER -