TY - GEN
T1 - Assisting refinement in system-on-chip design
AU - Mokrani, Hocine
AU - Ameur-Boulifa, Rabéa
AU - Encrenaz-Tiphene, Emmanuelle
PY - 2015/1/1
Y1 - 2015/1/1
N2 - With the increasing complexity of systems on chip, designers have adopted layered design methodologies, where the description of systems is made by steps. Currently, those methods do not ensure the preservation of properties in the process of system development. In this paper, we present a system on chip design method, based on model transformations-or refinements-in order to guarantee the preservation of functional correctness along the design flow. We also provide experimental results showing the benefits of the approach when property verification is concerned.
AB - With the increasing complexity of systems on chip, designers have adopted layered design methodologies, where the description of systems is made by steps. Currently, those methods do not ensure the preservation of properties in the process of system development. In this paper, we present a system on chip design method, based on model transformations-or refinements-in order to guarantee the preservation of functional correctness along the design flow. We also provide experimental results showing the benefits of the approach when property verification is concerned.
KW - Architecture exploration
KW - Communication refinement
KW - Formal verification
KW - Platform-Based Design (PBD)
KW - Property-preservation checking
KW - System modeling
KW - System on a Chip (SoC)
U2 - 10.1007/978-3-319-06317-1_2
DO - 10.1007/978-3-319-06317-1_2
M3 - Conference contribution
AN - SCOPUS:84906861330
SN - 9783319063164
T3 - Lecture Notes in Electrical Engineering
SP - 21
EP - 42
BT - Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2013
PB - Springer Verlag
T2 - Forum on Specification and Design Languages, FDL 2013
Y2 - 1 September 2013 through 1 September 2013
ER -