TY - GEN
T1 - Asymmetrical length biasing for energy efficient digital circuits
AU - Veirano, Francisco
AU - Silveira, Fernando
AU - Naviner, Lirida
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/6/13
Y1 - 2017/6/13
N2 - In this work we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies that minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results show that by using this sizing methodology, the energy per operation can be reduced more than 50% in a wide range of target performances. We used a 28nm UTBB FDSOI technology and we show that the combination of supply voltage scaling, back plane biasing and length biasing can be combined to obtain extremely energy efficient digital circuits.
AB - In this work we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies that minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results show that by using this sizing methodology, the energy per operation can be reduced more than 50% in a wide range of target performances. We used a 28nm UTBB FDSOI technology and we show that the combination of supply voltage scaling, back plane biasing and length biasing can be combined to obtain extremely energy efficient digital circuits.
UR - https://www.scopus.com/pages/publications/85022215494
U2 - 10.1109/LASCAS.2017.7948060
DO - 10.1109/LASCAS.2017.7948060
M3 - Conference contribution
AN - SCOPUS:85022215494
T3 - LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings
BT - LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 8th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2017
Y2 - 20 February 2017 through 23 February 2017
ER -