Automatic refinement checking for formal system models

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

For the design of complex systems, formal modeling languages such as UML or SysML find significant attention. The typical model-driven design flow assumes thereby an initial (abstract) model which is iteratively refined to a more precise description. During this process, new errors and inconsistencies might be introduced. In this paper, we propose an automatic method for verifying the consistency of refinements in UML or SysML. For this purpose, a theoretical foundation is considered from which the corresponding proof obligations are determined. Afterwards, they are encoded as an instance of Satisfiability Modulo Theories (SMT) and solved using proper solving engines. The practical use of the proposed method is demonstrated and compared to a previously proposed approach.

Original languageEnglish
Title of host publicationFDL 2014 - Proceedings of the 2014 Forum on Specification and Design Languages
EditorsAna Pinzari, Adam Morawiec
PublisherIEEE Computer Society
ISBN (Electronic)9791092279078
DOIs
Publication statusPublished - 5 Jun 2015
Externally publishedYes
Event17th Forum on Specification and Design Languages, FDL 2014 - Munich, Germany
Duration: 14 Oct 201416 Oct 2014

Publication series

NameForum on Specification and Design Languages
Volume2015-June
ISSN (Print)1636-9874

Conference

Conference17th Forum on Specification and Design Languages, FDL 2014
Country/TerritoryGermany
CityMunich
Period14/10/1416/10/14

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