Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security

Emna Amouri; Shivam Bhasin; Yves Mathieu; Tarik Graba; Jean Luc Danger; Habib Mehrez

doi:10.1109/FPL.2014.6927422

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security

Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean Luc Danger, Habib Mehrez

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The Tree-based FPGA offers better density and timing determinism than traditional mesh-based FPGA. Moreover, thanks to its multilevel structure, it offers greater easiness to balance dual signals in terms of routing resources number. In this paper, we study the use of the Wave Dynamic Differential Logic (WDDL) on a custom tree-based FPGA of 2048 cells. The WDDL technique offers an effective way to withstand Differential Power Attacks (DPA). However, the effectiveness of this countermeasure is guaranteed provided a symmetry is maintained between the routing of both the direct and complementary paths, which is very hard to achieve in FPGA. Thus, balancing aware Computer-Aided Design (CAD) tools must be developed. In this work, we propose first adjacent placement and balancing-aware routing techniques for tree-based FPGA to counter the routing unbalance. Then side channel analyses are performed on FPGA circuit implementing PRESENT crypto-processor. Experimental results show that the balancing methods enhance the design security against side channel attacks.

Original language	English
Title of host publication	Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9783000446450
DOIs	https://doi.org/10.1109/FPL.2014.6927422
Publication status	Published - 16 Oct 2014
Externally published	Yes
Event	24th International Conference on Field Programmable Logic and Applications, FPL 2014 - Munich, Germany Duration: 1 Sept 2014 → 5 Sept 2014

Publication series

Name	Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014

Conference

Conference	24th International Conference on Field Programmable Logic and Applications, FPL 2014
Country/Territory	Germany
City	Munich
Period	1/09/14 → 5/09/14

Keywords

Differential Power Analysis
Tree-based FPGA
WDDL
balance
placement
routing
security

Access to Document

10.1109/FPL.2014.6927422

Cite this

Amouri, E., Bhasin, S., Mathieu, Y., Graba, T., Danger, J. L., & Mehrez, H. (2014). Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. In Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 Article 6927422 (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL.2014.6927422

Amouri, Emna ; Bhasin, Shivam ; Mathieu, Yves et al. / Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 2014. (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014).

@inproceedings{1c7c329cd67e4790be0b10b563dec34e,

title = "Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security",

abstract = "The Tree-based FPGA offers better density and timing determinism than traditional mesh-based FPGA. Moreover, thanks to its multilevel structure, it offers greater easiness to balance dual signals in terms of routing resources number. In this paper, we study the use of the Wave Dynamic Differential Logic (WDDL) on a custom tree-based FPGA of 2048 cells. The WDDL technique offers an effective way to withstand Differential Power Attacks (DPA). However, the effectiveness of this countermeasure is guaranteed provided a symmetry is maintained between the routing of both the direct and complementary paths, which is very hard to achieve in FPGA. Thus, balancing aware Computer-Aided Design (CAD) tools must be developed. In this work, we propose first adjacent placement and balancing-aware routing techniques for tree-based FPGA to counter the routing unbalance. Then side channel analyses are performed on FPGA circuit implementing PRESENT crypto-processor. Experimental results show that the balancing methods enhance the design security against side channel attacks.",

keywords = "Differential Power Analysis, Tree-based FPGA, WDDL, balance, placement, routing, security",

author = "Emna Amouri and Shivam Bhasin and Yves Mathieu and Tarik Graba and Danger, \{Jean Luc\} and Habib Mehrez",

note = "Publisher Copyright: {\textcopyright} 2014 Technical University of Munich (TUM).; 24th International Conference on Field Programmable Logic and Applications, FPL 2014 ; Conference date: 01-09-2014 Through 05-09-2014",

year = "2014",

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doi = "10.1109/FPL.2014.6927422",

language = "English",

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Amouri, E, Bhasin, S, Mathieu, Y, Graba, T, Danger, JL & Mehrez, H 2014, Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014., 6927422, Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Institute of Electrical and Electronics Engineers Inc., 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 1/09/14. https://doi.org/10.1109/FPL.2014.6927422

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. / Amouri, Emna; Bhasin, Shivam; Mathieu, Yves et al.
Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6927422 (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Amouri, Emna

AU - Bhasin, Shivam

AU - Mathieu, Yves

AU - Graba, Tarik

AU - Danger, Jean Luc

AU - Mehrez, Habib

PY - 2014/10/16

Y1 - 2014/10/16

N2 - The Tree-based FPGA offers better density and timing determinism than traditional mesh-based FPGA. Moreover, thanks to its multilevel structure, it offers greater easiness to balance dual signals in terms of routing resources number. In this paper, we study the use of the Wave Dynamic Differential Logic (WDDL) on a custom tree-based FPGA of 2048 cells. The WDDL technique offers an effective way to withstand Differential Power Attacks (DPA). However, the effectiveness of this countermeasure is guaranteed provided a symmetry is maintained between the routing of both the direct and complementary paths, which is very hard to achieve in FPGA. Thus, balancing aware Computer-Aided Design (CAD) tools must be developed. In this work, we propose first adjacent placement and balancing-aware routing techniques for tree-based FPGA to counter the routing unbalance. Then side channel analyses are performed on FPGA circuit implementing PRESENT crypto-processor. Experimental results show that the balancing methods enhance the design security against side channel attacks.

AB - The Tree-based FPGA offers better density and timing determinism than traditional mesh-based FPGA. Moreover, thanks to its multilevel structure, it offers greater easiness to balance dual signals in terms of routing resources number. In this paper, we study the use of the Wave Dynamic Differential Logic (WDDL) on a custom tree-based FPGA of 2048 cells. The WDDL technique offers an effective way to withstand Differential Power Attacks (DPA). However, the effectiveness of this countermeasure is guaranteed provided a symmetry is maintained between the routing of both the direct and complementary paths, which is very hard to achieve in FPGA. Thus, balancing aware Computer-Aided Design (CAD) tools must be developed. In this work, we propose first adjacent placement and balancing-aware routing techniques for tree-based FPGA to counter the routing unbalance. Then side channel analyses are performed on FPGA circuit implementing PRESENT crypto-processor. Experimental results show that the balancing methods enhance the design security against side channel attacks.

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KW - Tree-based FPGA

KW - WDDL

KW - balance

KW - placement

KW - routing

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M3 - Conference contribution

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BT - Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 24th International Conference on Field Programmable Logic and Applications, FPL 2014

Y2 - 1 September 2014 through 5 September 2014

ER -

Amouri E, Bhasin S, Mathieu Y, Graba T, Danger JL, Mehrez H. Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. In Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6927422. (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014). doi: 10.1109/FPL.2014.6927422

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security

Abstract

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Keywords

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