Beyond 3G wideband and high linearity ADCs

This paper presents the challenges associated to the design of ADCs which must be compliant with 4G/LTE/LTE-A radio requirements. Primarily, the challenges are caused by increasing spectrum bandwidth, multi mode operation and the need of limiting the power consumption in the handset and in the base station. Therefore, wideband converters with high linearity (up to 100 dB of SFDR) and low power consumption (down to 0.5pJ by conversion step) are searched out with possibilities of reconfiguration to deal with the inherent trade-off between all these achievements. The paper gives an overview of the most common ADC architectures to achieve this goal: Flash, Pipeline, Successive Approximation and Sigma Delta ADCs. Then, efficient or still promising techniques are proposed to enhance performance. These techniques are mainly architectural innovations such as continuous time ΣΔ modulators and parallel architectures. The analog circuitry linearity tends to decrease due to the use of new advanced technologies, of increased speed and of simplification dictated by the need of power consumption reduction. However, an increasing use of calibration and digital correction allows both to compensate for the accuracy losses in analog circuitry and to reach higher performance.