Block turbo codes: From architecture to application

B. Geller; I. Diatta; J. P. Barbota; C. Vanstraceele; F. Rambeau

doi:10.1109/ISIT.2006.261747

Block turbo codes: From architecture to application

B. Geller
, I. Diatta
, J. P. Barbota
, C. Vanstraceele
, F. Rambeau

Paris-Saclay University
Université de PARIS XII

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper is concerned with the design of block turbo codes for very high bit rate applications. We first introduce an original low-complexity architecture designed for the iterative decoding of product codes. The implementation of the Chase-Pyndiah algorithm is simplified by not memorizing any of the list decoding concurrent code words. We then illustrate that such block turbo codes allow some bit rate improvement in the context of local loop transmission.

Original language	English
Title of host publication	Proceedings - 2006 IEEE International Symposium on Information Theory, ISIT 2006
Pages	1813-1816
Number of pages	4
DOIs	https://doi.org/10.1109/ISIT.2006.261747
Publication status	Published - 1 Dec 2006
Externally published	Yes
Event	2006 IEEE International Symposium on Information Theory, ISIT 2006 - Seattle, WA, United States Duration: 9 Jul 2006 → 14 Jul 2006

Publication series

Name	IEEE International Symposium on Information Theory - Proceedings
ISSN (Print)	2157-8101

Conference

Conference	2006 IEEE International Symposium on Information Theory, ISIT 2006
Country/Territory	United States
City	Seattle, WA
Period	9/07/06 → 14/07/06

Access to Document

10.1109/ISIT.2006.261747

Cite this

@inproceedings{934bb7d3951c496b9140c420241be932,

title = "Block turbo codes: From architecture to application",

abstract = "This paper is concerned with the design of block turbo codes for very high bit rate applications. We first introduce an original low-complexity architecture designed for the iterative decoding of product codes. The implementation of the Chase-Pyndiah algorithm is simplified by not memorizing any of the list decoding concurrent code words. We then illustrate that such block turbo codes allow some bit rate improvement in the context of local loop transmission.",

author = "B. Geller and I. Diatta and Barbota, \{J. P.\} and C. Vanstraceele and F. Rambeau",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/ISIT.2006.261747",

language = "English",

isbn = "1424405041",

series = "IEEE International Symposium on Information Theory - Proceedings",

pages = "1813--1816",

booktitle = "Proceedings - 2006 IEEE International Symposium on Information Theory, ISIT 2006",

note = "2006 IEEE International Symposium on Information Theory, ISIT 2006 ; Conference date: 09-07-2006 Through 14-07-2006",

}

Geller, B, Diatta, I, Barbota, JP, Vanstraceele, C & Rambeau, F 2006, Block turbo codes: From architecture to application. in Proceedings - 2006 IEEE International Symposium on Information Theory, ISIT 2006., 4036280, IEEE International Symposium on Information Theory - Proceedings, pp. 1813-1816, 2006 IEEE International Symposium on Information Theory, ISIT 2006, Seattle, WA, United States, 9/07/06. https://doi.org/10.1109/ISIT.2006.261747

Block turbo codes: From architecture to application. / Geller, B.; Diatta, I.; Barbota, J. P. et al.
Proceedings - 2006 IEEE International Symposium on Information Theory, ISIT 2006. 2006. p. 1813-1816 4036280 (IEEE International Symposium on Information Theory - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Block turbo codes

T2 - 2006 IEEE International Symposium on Information Theory, ISIT 2006

AU - Geller, B.

AU - Diatta, I.

AU - Barbota, J. P.

AU - Vanstraceele, C.

AU - Rambeau, F.

PY - 2006/12/1

Y1 - 2006/12/1

N2 - This paper is concerned with the design of block turbo codes for very high bit rate applications. We first introduce an original low-complexity architecture designed for the iterative decoding of product codes. The implementation of the Chase-Pyndiah algorithm is simplified by not memorizing any of the list decoding concurrent code words. We then illustrate that such block turbo codes allow some bit rate improvement in the context of local loop transmission.

AB - This paper is concerned with the design of block turbo codes for very high bit rate applications. We first introduce an original low-complexity architecture designed for the iterative decoding of product codes. The implementation of the Chase-Pyndiah algorithm is simplified by not memorizing any of the list decoding concurrent code words. We then illustrate that such block turbo codes allow some bit rate improvement in the context of local loop transmission.

U2 - 10.1109/ISIT.2006.261747

DO - 10.1109/ISIT.2006.261747

M3 - Conference contribution

AN - SCOPUS:39049084789

SN - 1424405041

SN - 9781424405046

T3 - IEEE International Symposium on Information Theory - Proceedings

SP - 1813

EP - 1816

BT - Proceedings - 2006 IEEE International Symposium on Information Theory, ISIT 2006

Y2 - 9 July 2006 through 14 July 2006

ER -

Block turbo codes: From architecture to application

Abstract

Publication series

Conference

Access to Document

Fingerprint

Cite this