TY - GEN
T1 - Classification of lightweight block ciphers for specific processor accelerated implementations
AU - Tehrani, Etienne
AU - Graba, Tarik
AU - Merabet, Abdelmalek Si
AU - Guilley, Sylvain
AU - Danger, Jean Luc
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/11/1
Y1 - 2019/11/1
N2 - Cryptography is a key element to the development of secure communication in embedded environments such as connected cars and IoT. For some specific applications specific Lightweight Block Ciphers (LBC) have emerged. Those algorithms have been designed to be less resource consuming and more flexible than standard cryptographic algorithms. In order to keep a high levels of performance for software implementation of those LBC, we propose to enhance the instruction set of microprocessors by adding custom instructions. This would allow the system designer to find the best compromise between flexibility requirements and efficiency in terms of throughput and latency. This paper first presents a classification of LBC according to their specific operations. Then, based on the open RISC-VISA, we propose a set of custom instructions to enhance LBC execution. The comparison of both execution time and throughput between different levels of processor customization is presented. Our results showed a significant gain as the execution time can be reduced by a factor between 20 and 100 for some classes of LBC.
AB - Cryptography is a key element to the development of secure communication in embedded environments such as connected cars and IoT. For some specific applications specific Lightweight Block Ciphers (LBC) have emerged. Those algorithms have been designed to be less resource consuming and more flexible than standard cryptographic algorithms. In order to keep a high levels of performance for software implementation of those LBC, we propose to enhance the instruction set of microprocessors by adding custom instructions. This would allow the system designer to find the best compromise between flexibility requirements and efficiency in terms of throughput and latency. This paper first presents a classification of LBC according to their specific operations. Then, based on the open RISC-VISA, we propose a set of custom instructions to enhance LBC execution. The comparison of both execution time and throughput between different levels of processor customization is presented. Our results showed a significant gain as the execution time can be reduced by a factor between 20 and 100 for some classes of LBC.
KW - Cryptographic extension
KW - Lightweight cryptography
KW - Performance
KW - RISC-V
UR - https://www.scopus.com/pages/publications/85079148164
U2 - 10.1109/ICECS46596.2019.8965156
DO - 10.1109/ICECS46596.2019.8965156
M3 - Conference contribution
AN - SCOPUS:85079148164
T3 - 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
SP - 747
EP - 750
BT - 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
Y2 - 27 November 2019 through 29 November 2019
ER -