Clock distribution network for microprocessors

A. Klisnick; J. Kuba; D. Ros; A. Carillon; G. Jamelot; R. Smith; F. Strati; G. J. Tallents; R. Keenan; S. J. Topping; C. L.S. Lewis; P. Nickles; K. A. Janulewicz; F. Bortolotto; D. Neely; R. Clarke; J. Collier; A. G. MacPhee; C. Chenais-Popovics; J. C. Chanteloup; D. Joyeux; D. Phalippou; H. Daido; H. Tang

D. Joyeux, D. Phalippou, H. Daido, H. Tang

Laboratoire de Spectroscopie Atomique et Ionique
Université Paris-Saclay
Czech Technical University in Prague
Lawrence Livermore National Laboratory
Department of Physics
University of York
School of Mathematics and Physics
Queen's University of Belfast
Max-Born-Institute
CCLRC Rutherford Appleton Laboratory
Institut d’Optique ThéOrique et Appliquée
Centre national de la recherche scientifique
Japan Atom. Ener. Research Institute
Japan Atomic Energy Agency

Research output: Contribution to journal › Article › peer-review

15 Citations (Scopus)

Abstract

A global clock distribution strategy implemented on several microprocessor chips is described. The clock network consists of buffered, tunable tree networks, with the final trees all driving a common grid. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune a single interconnect network with 6 meters of wire and 50,000 resistors, capacitors, and inductors. Global clock skew as low as 22 ps was measured for large microprocessor chips.

Original language	English
Pages (from-to)	184-187
Number of pages	4
Journal	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Publication status	Published - 1 Jan 2000

Cite this

Klisnick, A., Kuba, J., Ros, D., Carillon, A., Jamelot, G., Smith, R., Strati, F., Tallents, G. J., Keenan, R., Topping, S. J., Lewis, C. L. S., Nickles, P., Janulewicz, K. A., Bortolotto, F., Neely, D., Clarke, R., Collier, J., MacPhee, A. G., Chenais-Popovics, C., ... Tang, H. (2000). Clock distribution network for microprocessors. IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 184-187.

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title = "Clock distribution network for microprocessors",

abstract = "A global clock distribution strategy implemented on several microprocessor chips is described. The clock network consists of buffered, tunable tree networks, with the final trees all driving a common grid. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune a single interconnect network with 6 meters of wire and 50,000 resistors, capacitors, and inductors. Global clock skew as low as 22 ps was measured for large microprocessor chips.",

author = "A. Klisnick and J. Kuba and D. Ros and A. Carillon and G. Jamelot and R. Smith and F. Strati and Tallents, \{G. J.\} and R. Keenan and Topping, \{S. J.\} and Lewis, \{C. L.S.\} and P. Nickles and Janulewicz, \{K. A.\} and F. Bortolotto and D. Neely and R. Clarke and J. Collier and MacPhee, \{A. G.\} and C. Chenais-Popovics and Chanteloup, \{J. C.\} and D. Joyeux and D. Phalippou and H. Daido and H. Tang",

year = "2000",

month = jan,

day = "1",

language = "English",

pages = "184--187",

journal = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

}

Klisnick, A, Kuba, J, Ros, D, Carillon, A, Jamelot, G, Smith, R, Strati, F, Tallents, GJ, Keenan, R, Topping, SJ, Lewis, CLS, Nickles, P, Janulewicz, KA, Bortolotto, F, Neely, D, Clarke, R, Collier, J, MacPhee, AG, Chenais-Popovics, C, Chanteloup, JC, Joyeux, D, Phalippou, D, Daido, H & Tang, H 2000, 'Clock distribution network for microprocessors', IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 184-187.

TY - JOUR

T1 - Clock distribution network for microprocessors

AU - Klisnick, A.

AU - Kuba, J.

AU - Ros, D.

AU - Carillon, A.

AU - Jamelot, G.

AU - Smith, R.

AU - Strati, F.

AU - Tallents, G. J.

AU - Keenan, R.

AU - Topping, S. J.

AU - Lewis, C. L.S.

AU - Nickles, P.

AU - Janulewicz, K. A.

AU - Bortolotto, F.

AU - Neely, D.

AU - Clarke, R.

AU - Collier, J.

AU - MacPhee, A. G.

AU - Chenais-Popovics, C.

AU - Chanteloup, J. C.

AU - Joyeux, D.

AU - Phalippou, D.

AU - Daido, H.

AU - Tang, H.

PY - 2000/1/1

Y1 - 2000/1/1

N2 - A global clock distribution strategy implemented on several microprocessor chips is described. The clock network consists of buffered, tunable tree networks, with the final trees all driving a common grid. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune a single interconnect network with 6 meters of wire and 50,000 resistors, capacitors, and inductors. Global clock skew as low as 22 ps was measured for large microprocessor chips.

AB - A global clock distribution strategy implemented on several microprocessor chips is described. The clock network consists of buffered, tunable tree networks, with the final trees all driving a common grid. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune a single interconnect network with 6 meters of wire and 50,000 resistors, capacitors, and inductors. Global clock skew as low as 22 ps was measured for large microprocessor chips.

M3 - Article

AN - SCOPUS:0033719722

SP - 184

EP - 187

JO - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

JF - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

ER -

Clock distribution network for microprocessors

Abstract

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