CMOS structures suitable for secured hardware

Sylvain Guilley; Philippe Hoogvorst; Yves Mathieu; Renaud Pacalet; Jean Provost

doi:10.1109/DATE.2004.1269113

CMOS structures suitable for secured hardware

Sylvain Guilley
, Philippe Hoogvorst
, Yves Mathieu
, Renaud Pacalet
, Jean Provost

CNRS LTCI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.

Original language	English
Title of host publication	Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
Editors	G. Gielen, J. Figueras
Pages	1414-1415
Number of pages	2
DOIs	https://doi.org/10.1109/DATE.2004.1269113
Publication status	Published - 12 Jul 2004
Externally published	Yes
Event	Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 - Paris, France Duration: 16 Feb 2004 → 20 Feb 2004

Publication series

Name	Proceedings - Design, Automation and Test in Europe Conference and Exhibition
Volume	2

Conference

Conference	Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
Country/Territory	France
City	Paris
Period	16/02/04 → 20/02/04

Access to Document

10.1109/DATE.2004.1269113

Cite this

Guilley, S., Hoogvorst, P., Mathieu, Y., Pacalet, R., & Provost, J. (2004). CMOS structures suitable for secured hardware. In G. Gielen, & J. Figueras (Eds.), Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 (pp. 1414-1415). (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; Vol. 2). https://doi.org/10.1109/DATE.2004.1269113

@inproceedings{1341c4d6fbfe42f9ab8ab381344345ad,

title = "CMOS structures suitable for secured hardware",

abstract = "Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.",

author = "Sylvain Guilley and Philippe Hoogvorst and Yves Mathieu and Renaud Pacalet and Jean Provost",

year = "2004",

month = jul,

day = "12",

doi = "10.1109/DATE.2004.1269113",

language = "English",

isbn = "0769520855",

series = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition",

pages = "1414--1415",

editor = "G. Gielen and J. Figueras",

booktitle = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04",

note = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 ; Conference date: 16-02-2004 Through 20-02-2004",

}

Guilley, S, Hoogvorst, P, Mathieu, Y, Pacalet, R & Provost, J 2004, CMOS structures suitable for secured hardware. in G Gielen & J Figueras (eds), Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 1414-1415, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, France, 16/02/04. https://doi.org/10.1109/DATE.2004.1269113

CMOS structures suitable for secured hardware. / Guilley, Sylvain; Hoogvorst, Philippe; Mathieu, Yves et al.
Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. ed. / G. Gielen; J. Figueras. 2004. p. 1414-1415 (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - CMOS structures suitable for secured hardware

AU - Guilley, Sylvain

AU - Hoogvorst, Philippe

AU - Mathieu, Yves

AU - Pacalet, Renaud

AU - Provost, Jean

PY - 2004/7/12

Y1 - 2004/7/12

N2 - Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.

AB - Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.

UR - https://www.scopus.com/pages/publications/3042609835

U2 - 10.1109/DATE.2004.1269113

DO - 10.1109/DATE.2004.1269113

M3 - Conference contribution

AN - SCOPUS:3042609835

SN - 0769520855

SN - 9780769520858

T3 - Proceedings - Design, Automation and Test in Europe Conference and Exhibition

SP - 1414

EP - 1415

BT - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04

A2 - Gielen, G.

A2 - Figueras, J.

T2 - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04

Y2 - 16 February 2004 through 20 February 2004

ER -

CMOS structures suitable for secured hardware

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this