Comparative study of defect-tolerant multiplexers for FPGAs

As CMOS technology enters the nanometer regime, manufacturing defects are becoming a challenging concern in current and future technologies. This work aims at improving defect tolerance in FPGAs which are certainly affected by technology downsizing. Since the cornerstone of the FPGA logic and interconnect resources is the multiplexer, we compare different hardened architectures of the multiplexer in terms of robustness, area, power and delay, in order to select the most convenient one according to a design metric we define. The architectures are studied under single defect injection by a tool that models several possible defects for a given design according to its extracted netlist. Eventually, the robustness gain using the chosen multiplexer is assessed for different sizes of FPGA look-up tables.