Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs

Arwa Ben Dhia; Lirida Naviner; Philippe Matherat

doi:10.1109/LATW.2013.6562661

Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs

Arwa Ben Dhia
, Lirida Naviner
, Philippe Matherat

CNRS LTCI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper first introduces three new architectures of a voter for a Butterfly CLB in an SRAM-based FPGA. Taking into account area and delay constraints, an optimized voter architecture is picked up for the Butterfly design. Another version for the latter is also proposed in order to reduce the area overhead. Afterward, we synthesize different CLB fabless architectures in STM 65nm CMOS technology and evaluate their fault tolerance and reliability, so as to obtain an overview of the current state of the art. Finally, we compare the CLB architectures with respect to the conventional one by defining a metric expressing the tradeoff between the fault tolerance gain, the performance degradation and the cost penalties including area, power and SRAM memory.

Original language	English
Title of host publication	LATW 2013 - 14th IEEE Latin-American Test Workshop
DOIs	https://doi.org/10.1109/LATW.2013.6562661
Publication status	Published - 2 Sept 2013
Externally published	Yes
Event	14th IEEE Latin-American Test Workshop, LATW 2013 - Cordoba, Argentina Duration: 3 Apr 2013 → 5 Apr 2013

Publication series

Name	LATW 2013 - 14th IEEE Latin-American Test Workshop

Conference

Conference	14th IEEE Latin-American Test Workshop, LATW 2013
Country/Territory	Argentina
City	Cordoba
Period	3/04/13 → 5/04/13

Keywords

CLB
Look-up Table (LUT)
SRAM-based FPGA
fault tolerance
hardening techniques
logical masking
reliability

Access to Document

10.1109/LATW.2013.6562661

Cite this

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title = "Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs",

abstract = "This paper first introduces three new architectures of a voter for a Butterfly CLB in an SRAM-based FPGA. Taking into account area and delay constraints, an optimized voter architecture is picked up for the Butterfly design. Another version for the latter is also proposed in order to reduce the area overhead. Afterward, we synthesize different CLB fabless architectures in STM 65nm CMOS technology and evaluate their fault tolerance and reliability, so as to obtain an overview of the current state of the art. Finally, we compare the CLB architectures with respect to the conventional one by defining a metric expressing the tradeoff between the fault tolerance gain, the performance degradation and the cost penalties including area, power and SRAM memory.",

keywords = "CLB, Look-up Table (LUT), SRAM-based FPGA, fault tolerance, hardening techniques, logical masking, reliability",

author = "Dhia, \{Arwa Ben\} and Lirida Naviner and Philippe Matherat",

year = "2013",

month = sep,

day = "2",

doi = "10.1109/LATW.2013.6562661",

language = "English",

isbn = "9781479905973",

series = "LATW 2013 - 14th IEEE Latin-American Test Workshop",

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note = "14th IEEE Latin-American Test Workshop, LATW 2013 ; Conference date: 03-04-2013 Through 05-04-2013",

}

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AU - Dhia, Arwa Ben

AU - Naviner, Lirida

AU - Matherat, Philippe

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Y1 - 2013/9/2

N2 - This paper first introduces three new architectures of a voter for a Butterfly CLB in an SRAM-based FPGA. Taking into account area and delay constraints, an optimized voter architecture is picked up for the Butterfly design. Another version for the latter is also proposed in order to reduce the area overhead. Afterward, we synthesize different CLB fabless architectures in STM 65nm CMOS technology and evaluate their fault tolerance and reliability, so as to obtain an overview of the current state of the art. Finally, we compare the CLB architectures with respect to the conventional one by defining a metric expressing the tradeoff between the fault tolerance gain, the performance degradation and the cost penalties including area, power and SRAM memory.

AB - This paper first introduces three new architectures of a voter for a Butterfly CLB in an SRAM-based FPGA. Taking into account area and delay constraints, an optimized voter architecture is picked up for the Butterfly design. Another version for the latter is also proposed in order to reduce the area overhead. Afterward, we synthesize different CLB fabless architectures in STM 65nm CMOS technology and evaluate their fault tolerance and reliability, so as to obtain an overview of the current state of the art. Finally, we compare the CLB architectures with respect to the conventional one by defining a metric expressing the tradeoff between the fault tolerance gain, the performance degradation and the cost penalties including area, power and SRAM memory.

KW - CLB

KW - Look-up Table (LUT)

KW - SRAM-based FPGA

KW - fault tolerance

KW - hardening techniques

KW - logical masking

KW - reliability

UR - https://www.scopus.com/pages/publications/84883096485

U2 - 10.1109/LATW.2013.6562661

DO - 10.1109/LATW.2013.6562661

M3 - Conference contribution

AN - SCOPUS:84883096485

SN - 9781479905973

T3 - LATW 2013 - 14th IEEE Latin-American Test Workshop

BT - LATW 2013 - 14th IEEE Latin-American Test Workshop

T2 - 14th IEEE Latin-American Test Workshop, LATW 2013

Y2 - 3 April 2013 through 5 April 2013

ER -

Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs

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Keywords

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