Convolution blocks based on self-checking operators

The arrival of CMOS integrated systems into nanoscale dimensions is presenting many challenges to designers and manufacturers concerning yield and reliability of integrated circuits. Traditional techniques to cope with these subjects are not as effective as they were before and many solutions are considered to allow CMOS evolution to continue according to Moore's law. Among the proposed solutions in the literature there's self-checking design and circuit reconfiguration. In the present work we introduce self-checking arithmetic operators in the design of convolution processors and we verify the penalties of such solutions in terms of area and speed. The self-checking methods considered are parity prediction, duplication and 1-out-of-3 encoding.