@inproceedings{08e32852ddb14a6db4952abcbccc1d4d,
title = "Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA",
abstract = "The Wave Dynamic Differential Logic (WDDL) offers an effective way to resist Side Channel Attacks (SCA). But, it suffers from early propagation and routing imbalance between dual signals. In this paper, we deal first with the EPE problem. We study the security of BCDL logic, which is known to counter early propagation, and we compare it to WDDL logic. We target a custom tree-based FPGA of 2048 cells. Next, we try to solve the routing imbalance problem by performing an adjacent placement and a timing balance driven routing. Side channel analyses are performed on FPGA circuit implementing PRESENT crypto-processor. Experimental results show that both avoiding early propagation and diminishing routing imbalance by controlling placement and routing tools enhance the design security against SCA.",
keywords = "Dual-rail Precharge Logic (DPL), FPGA, Side Channel Attacks, placement, routing",
author = "Emna Amouri and Shivam Bhasin and Yves Mathieu and Tarik Graba and Danger, \{Jean Luc\}",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; International Conference on IC Design and Technology, ICICDT 2015 ; Conference date: 01-06-2015 Through 03-06-2015",
year = "2015",
month = jul,
day = "23",
doi = "10.1109/ICICDT.2015.7165897",
language = "English",
series = "2015 International Conference on IC Design and Technology, ICICDT 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 International Conference on IC Design and Technology, ICICDT 2015",
}