Criteria for improved open-circuit voltage in a-Si:H (N) c-Si (P) front heterojunction with intrinsic thin layer solar cells

Hydrog enated amorphouscrystalline silicon "heterojunction with intrinsic thin layer (HIT)" solar cells have gained popularity after it was demonstrated by Sanyo that they can achieve stable conversion efficiencies, as high as crystalline silicon (c-Si) cells, but where the cost may be reduced with the help of amorphous silicon (a-Si:H) low temperature deposition technology. In this article, we study N-a-Si:HP-c-Si front HIT structures, where light enters through the N-a-Si:H layer. The aim is to examine ways of improving the open-circuit voltage, using computer modeling in conjunction with experiments. We also assess under which conditions such improvements in Voc actually occur. Modeling indicates that for a density of states Nss 1013 cm-2 on the surface of the P-c-Si wafer facing the emitter layer, Voc is entirely limited by this parameter and is lower than 0.5 V. We also learn that it is possible to increase the Voc to ∼0.73 V by reducing this defect density to ∼ 1010 cm-2, by reducing the surface recombination speed of the electrons at the back P-c-Si aluminum contact (SnL), and by improving the lifetime of the carriers (τ) in the P-c-Si wafer to ∼5 ms. Modeling further indicates that when τ≤0.1 ms, the sensitivity of Voc to SnL vanishes, as very few back-diffusing electrons can reach the back contact. Improvements in Voc by decreasing both the defect density on the surface of the P-c-Si wafer facing the emitter layer and SnL have been achieved in practice by (a) improved passivation thanks to a thin intrinsic polymorphous silicon layer deposited on the c-Si wafer (instead of a-Si:H) and (b) using localized aluminum and back surface field layers to attain a lower SnL. Experimentally, a Voc of 0.675 V has already been attained. Simulations indicate that the lifetime of carriers inside the P-c-Si wafer of these cells is ∼366 μs and needs to be improved to achieve a higher Voc.