Cross logic: A new approach for defect-tolerant circuits

Mariem Slimani; Arwa Ben Dhia; Lirida Naviner

doi:10.1109/ICICDT.2014.6838602

Cross logic: A new approach for defect-tolerant circuits

Mariem Slimani, Arwa Ben Dhia, Lirida Naviner

CNRS LTCI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

As technology scales down to the nanometer era, manufacturing defects are rapidly becoming a major concern in the design of electronic circuits. In this work, we present a defect-tolerant logic family constructed with CMOS cells. The basic idea of this approach is the construction of logic gates in which the outputs and their complementaries correct each other. We demonstrate, through circuit simulation using CMOS cells from a 65nm industrial process, that the proposed logic turns out to be a good compromise to construct robust circuits under the constraint of limited area overhead.

Original language	English
Title of host publication	ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology
Publisher	IEEE Computer Society
ISBN (Print)	9781479921539
DOIs	https://doi.org/10.1109/ICICDT.2014.6838602
Publication status	Published - 1 Jan 2014
Externally published	Yes
Event	2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014 - Austin, TX, United States Duration: 28 May 2014 → 30 May 2014

Publication series

Name	ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology

Conference

Conference	2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014
Country/Territory	United States
City	Austin, TX
Period	28/05/14 → 30/05/14

Keywords

Robustness
analog fault simulation
defect modeling
defect tolerance

Access to Document

10.1109/ICICDT.2014.6838602

Cite this

Slimani, M., Ben Dhia, A., & Naviner, L. (2014). Cross logic: A new approach for defect-tolerant circuits. In ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology Article 6838602 (ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology). IEEE Computer Society. https://doi.org/10.1109/ICICDT.2014.6838602

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title = "Cross logic: A new approach for defect-tolerant circuits",

abstract = "As technology scales down to the nanometer era, manufacturing defects are rapidly becoming a major concern in the design of electronic circuits. In this work, we present a defect-tolerant logic family constructed with CMOS cells. The basic idea of this approach is the construction of logic gates in which the outputs and their complementaries correct each other. We demonstrate, through circuit simulation using CMOS cells from a 65nm industrial process, that the proposed logic turns out to be a good compromise to construct robust circuits under the constraint of limited area overhead.",

keywords = "Robustness, analog fault simulation, defect modeling, defect tolerance",

author = "Mariem Slimani and \{Ben Dhia\}, Arwa and Lirida Naviner",

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doi = "10.1109/ICICDT.2014.6838602",

language = "English",

isbn = "9781479921539",

series = "ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology",

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booktitle = "ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology",

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Slimani, M, Ben Dhia, A & Naviner, L 2014, Cross logic: A new approach for defect-tolerant circuits. in ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology., 6838602, ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology, IEEE Computer Society, 2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014, Austin, TX, United States, 28/05/14. https://doi.org/10.1109/ICICDT.2014.6838602

Cross logic: A new approach for defect-tolerant circuits. / Slimani, Mariem; Ben Dhia, Arwa; Naviner, Lirida.
ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology. IEEE Computer Society, 2014. 6838602 (ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Slimani, Mariem

AU - Ben Dhia, Arwa

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N2 - As technology scales down to the nanometer era, manufacturing defects are rapidly becoming a major concern in the design of electronic circuits. In this work, we present a defect-tolerant logic family constructed with CMOS cells. The basic idea of this approach is the construction of logic gates in which the outputs and their complementaries correct each other. We demonstrate, through circuit simulation using CMOS cells from a 65nm industrial process, that the proposed logic turns out to be a good compromise to construct robust circuits under the constraint of limited area overhead.

AB - As technology scales down to the nanometer era, manufacturing defects are rapidly becoming a major concern in the design of electronic circuits. In this work, we present a defect-tolerant logic family constructed with CMOS cells. The basic idea of this approach is the construction of logic gates in which the outputs and their complementaries correct each other. We demonstrate, through circuit simulation using CMOS cells from a 65nm industrial process, that the proposed logic turns out to be a good compromise to construct robust circuits under the constraint of limited area overhead.

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KW - analog fault simulation

KW - defect modeling

KW - defect tolerance

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DO - 10.1109/ICICDT.2014.6838602

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T3 - ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology

BT - ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology

PB - IEEE Computer Society

Y2 - 28 May 2014 through 30 May 2014

ER -

Cross logic: A new approach for defect-tolerant circuits

Abstract

Publication series

Conference

Keywords

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