Cryogenic In-MRAM Computing

In the computation storage separated von-Neumann architecture, memory-wall becomes critical due to large access latency and tremendous amount of data movement. In this work, we pursue cryogenic temperature based memory design and focus on spin-transfer-torque magnetoresistive random access memory (STT-MRAM) at 77-Kelvin (achieved with low-cost liquid nitrogen). Cryogenic compact model and related cryogenic bit-cell are investigated based on 77K experiment data of magnetic tunnel junction (MTJ) and CMOS transistor. Aggressive energy reduction is obtained through in-MRAM computing architecture. A 1Kb sub-array is simulated based on above cryogenic models. Results show that cryogenic in-MRAM computing provides performance improvements of 32% on average, and concurrently reduces memory energy consumption by 19% on average. Compared with room temperature (RT) simulation results, a 70% reduction of sensing latency is realized at 0.7-V supply voltage, with the cost of 30% increased writing latency and 20% higher energy consumption. A 32.5% sensing failure probability is alleviated in the 77K cryogenic environment. The proposed 77K cryogenic design methodology can be further applied to energy constrained applications.