Delay-reduction technique for DWA algorithms

Chadi Jabbour; Hussein Fakhoury; Van Tam Nguyen; Patrick Loumeau

doi:10.1109/TCSII.2014.2335437

Delay-reduction technique for DWA algorithms

Chadi Jabbour
, Hussein Fakhoury
, Van Tam Nguyen
, Patrick Loumeau

Research output: Contribution to journal › Article › peer-review

Abstract

This brief presents a delay-reduction technique for data weighted averaging (DWA) algorithms. The proposed technique is based on quantizing the shift pointer of the DWA circuit, which leads to a complexity reduction of the shuffler and, consequently, to a delay reduction as well. Synthesis results in a 65-nm CMOS process show that the proposed technique reduces DWA delay below 100 ps for a 5-bit delta-sigma modulator. The proposed technique reduces the DWA in-band tones that arise as well, particularly for low input amplitudes.

Original language	English
Article number	2335437
Pages (from-to)	733-737
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	61
Issue number	10
DOIs	https://doi.org/10.1109/TCSII.2014.2335437
Publication status	Published - 1 Oct 2014

Keywords

Analog-to-digital converter (ADC)
Data weighted averaging (DWA)
Delta-sigma (ΔΣ) modulator
Digital-to-analog converter (DAC) linearization

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10.1109/TCSII.2014.2335437

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title = "Delay-reduction technique for DWA algorithms",

abstract = "This brief presents a delay-reduction technique for data weighted averaging (DWA) algorithms. The proposed technique is based on quantizing the shift pointer of the DWA circuit, which leads to a complexity reduction of the shuffler and, consequently, to a delay reduction as well. Synthesis results in a 65-nm CMOS process show that the proposed technique reduces DWA delay below 100 ps for a 5-bit delta-sigma modulator. The proposed technique reduces the DWA in-band tones that arise as well, particularly for low input amplitudes.",

keywords = "Analog-to-digital converter (ADC), Data weighted averaging (DWA), Delta-sigma (ΔΣ) modulator, Digital-to-analog converter (DAC) linearization",

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AU - Loumeau, Patrick

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AB - This brief presents a delay-reduction technique for data weighted averaging (DWA) algorithms. The proposed technique is based on quantizing the shift pointer of the DWA circuit, which leads to a complexity reduction of the shuffler and, consequently, to a delay reduction as well. Synthesis results in a 65-nm CMOS process show that the proposed technique reduces DWA delay below 100 ps for a 5-bit delta-sigma modulator. The proposed technique reduces the DWA in-band tones that arise as well, particularly for low input amplitudes.

KW - Analog-to-digital converter (ADC)

KW - Data weighted averaging (DWA)

KW - Delta-sigma (ΔΣ) modulator

KW - Digital-to-analog converter (DAC) linearization

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JF - IEEE Transactions on Circuits and Systems II: Express Briefs

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ER -

Delay-reduction technique for DWA algorithms

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