Design and implementation of cascade decimation filter for radio communications

Khaled Grati; Adel Ghazel; Lirida Naviner; Faker Moatamri

Design and implementation of cascade decimation filter for radio communications

Khaled Grati
, Adel Ghazel
, Lirida Naviner
, Faker Moatamri

University of Carthage, Ecole Supérieure des Communications de Tunis

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Citations (Scopus)

Abstract

This paper describes the design of a decimation filter for use with a 4^th order bandpass ΣΔ modulator adapted for multi-standards wireless transceiver. The simulations undertaken demonstrated that GSM and DECT standards specifications are met by a filtering cascade structure composed of 5^th order comb filter, 2 half-band filter stages and a droop-correction filter. A fixed-point architectural design was defined and low-power FPGA implementation results are reported.

Original language	English
Title of host publication	ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
Pages	1603-1606
Number of pages	4
Publication status	Published - 1 Dec 2001
Event	8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , Malta Duration: 2 Sept 2001 → 5 Sept 2001

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	3

Conference

Conference	8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
Country/Territory	Malta
Period	2/09/01 → 5/09/01

Cite this

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title = "Design and implementation of cascade decimation filter for radio communications",

abstract = "This paper describes the design of a decimation filter for use with a 4th order bandpass ΣΔ modulator adapted for multi-standards wireless transceiver. The simulations undertaken demonstrated that GSM and DECT standards specifications are met by a filtering cascade structure composed of 5th order comb filter, 2 half-band filter stages and a droop-correction filter. A fixed-point architectural design was defined and low-power FPGA implementation results are reported.",

author = "Khaled Grati and Adel Ghazel and Lirida Naviner and Faker Moatamri",

year = "2001",

month = dec,

day = "1",

language = "English",

isbn = "0780370570",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

pages = "1603--1606",

booktitle = "ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems",

note = "8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 ; Conference date: 02-09-2001 Through 05-09-2001",

}

Grati, K, Ghazel, A, Naviner, L & Moatamri, F 2001, Design and implementation of cascade decimation filter for radio communications. in ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems., 957524, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 3, pp. 1603-1606, 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, 2/09/01.

Design and implementation of cascade decimation filter for radio communications. / Grati, Khaled; Ghazel, Adel; Naviner, Lirida et al.
ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. 2001. p. 1603-1606 957524 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design and implementation of cascade decimation filter for radio communications

AU - Grati, Khaled

AU - Ghazel, Adel

AU - Naviner, Lirida

AU - Moatamri, Faker

PY - 2001/12/1

Y1 - 2001/12/1

N2 - This paper describes the design of a decimation filter for use with a 4th order bandpass ΣΔ modulator adapted for multi-standards wireless transceiver. The simulations undertaken demonstrated that GSM and DECT standards specifications are met by a filtering cascade structure composed of 5th order comb filter, 2 half-band filter stages and a droop-correction filter. A fixed-point architectural design was defined and low-power FPGA implementation results are reported.

AB - This paper describes the design of a decimation filter for use with a 4th order bandpass ΣΔ modulator adapted for multi-standards wireless transceiver. The simulations undertaken demonstrated that GSM and DECT standards specifications are met by a filtering cascade structure composed of 5th order comb filter, 2 half-band filter stages and a droop-correction filter. A fixed-point architectural design was defined and low-power FPGA implementation results are reported.

M3 - Conference contribution

AN - SCOPUS:27944477479

SN - 0780370570

SN - 9780780370579

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

SP - 1603

EP - 1606

BT - ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems

T2 - 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001

Y2 - 2 September 2001 through 5 September 2001

ER -

Design and implementation of cascade decimation filter for radio communications

Abstract

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