Design and implementation of cascade decimation filter for radio communications

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Abstract

This paper describes the design of a decimation filter for use with a 4th order bandpass ΣΔ modulator adapted for multi-standards wireless transceiver. The simulations undertaken demonstrated that GSM and DECT standards specifications are met by a filtering cascade structure composed of 5th order comb filter, 2 half-band filter stages and a droop-correction filter. A fixed-point architectural design was defined and low-power FPGA implementation results are reported.

Original languageEnglish
Title of host publicationICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
Pages1603-1606
Number of pages4
Publication statusPublished - 1 Dec 2001
Event8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , Malta
Duration: 2 Sept 20015 Sept 2001

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume3

Conference

Conference8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
Country/TerritoryMalta
Period2/09/015/09/01

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