Design and prototyping of a ΣΔ decimator filter for DECT standard

L. Naviner; J. F. Naviner; H. Petit; P. Loumeau

Design and prototyping of a ΣΔ decimator filter for DECT standard

L. Naviner
, J. F. Naviner
, H. Petit
, P. Loumeau

Telecom Paris

Research output: Contribution to conference › Paper › peer-review

Abstract

This work deals with the design and prototyping of a decimation filter for DECT standard. Efficient implementation is obtained with a careful design of the filter and a FPGA structure oriented VHDL modelling, reducing power computation and routing needs. A filter prototype has been implemented in a programmable Altera circuit FLEX10K20.

Original language	English
Pages	698-701
Number of pages	4
Publication status	Published - 1 Dec 2000
Event	43rd Midwest Circuits and Systems Conference (MWSCAS-2000) - Lansing, MI, United States Duration: 8 Aug 2000 → 11 Aug 2000

Conference

Conference	43rd Midwest Circuits and Systems Conference (MWSCAS-2000)
Country/Territory	United States
City	Lansing, MI
Period	8/08/00 → 11/08/00

Cite this

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title = "Design and prototyping of a ΣΔ decimator filter for DECT standard",

abstract = "This work deals with the design and prototyping of a decimation filter for DECT standard. Efficient implementation is obtained with a careful design of the filter and a FPGA structure oriented VHDL modelling, reducing power computation and routing needs. A filter prototype has been implemented in a programmable Altera circuit FLEX10K20.",

author = "L. Naviner and Naviner, \{J. F.\} and H. Petit and P. Loumeau",

year = "2000",

month = dec,

day = "1",

language = "English",

pages = "698--701",

note = "43rd Midwest Circuits and Systems Conference (MWSCAS-2000) ; Conference date: 08-08-2000 Through 11-08-2000",

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T1 - Design and prototyping of a ΣΔ decimator filter for DECT standard

AU - Naviner, L.

AU - Naviner, J. F.

AU - Petit, H.

AU - Loumeau, P.

PY - 2000/12/1

Y1 - 2000/12/1

N2 - This work deals with the design and prototyping of a decimation filter for DECT standard. Efficient implementation is obtained with a careful design of the filter and a FPGA structure oriented VHDL modelling, reducing power computation and routing needs. A filter prototype has been implemented in a programmable Altera circuit FLEX10K20.

AB - This work deals with the design and prototyping of a decimation filter for DECT standard. Efficient implementation is obtained with a careful design of the filter and a FPGA structure oriented VHDL modelling, reducing power computation and routing needs. A filter prototype has been implemented in a programmable Altera circuit FLEX10K20.

M3 - Paper

AN - SCOPUS:0034464327

SP - 698

EP - 701

T2 - 43rd Midwest Circuits and Systems Conference (MWSCAS-2000)

Y2 - 8 August 2000 through 11 August 2000

ER -

Design and prototyping of a ΣΔ decimator filter for DECT standard

Abstract

Conference

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