Design methodology of an ASIC TRNG based on an open-loop delay chain

Molka Ben-Romdhane, Tarik Graba, Jean Luc Danger, Yves Mathieu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Many applications require unpredictable randomly generated numbers. This paper presents a lightweight architecture of a high speed true random number generator (TRNG) and its ASIC implementation. The proposed TRNG randomness is extracted from the observation of the final state of a chain of bistable elements after putting them in a metastable state. The ASIC design methodology targets the CMOS 65 nm technology from STMicroelectronics (STM). It allows to validate the TRNG behavior and evaluate the randomness in different working conditions. Results of standard statistical tests are also presented to validate the TRNG ASIC structure.

Original languageEnglish
Title of host publication2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013
DOIs
Publication statusPublished - 10 Sept 2013
Externally publishedYes
Event2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013 - Paris, France
Duration: 16 Jun 201319 Jun 2013

Publication series

Name2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013

Conference

Conference2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013
Country/TerritoryFrance
CityParis
Period16/06/1319/06/13

Keywords

  • ASIC
  • TRNG
  • delay control
  • metastability

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